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Commit 33c7c7b7 authored by Felipe Balbi's avatar Felipe Balbi Committed by Tony Lindgren
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arm: omap: irq: define INTC_ILR0 register 



this is currently used as a hardcoded 0x100
offset.

Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 176da6c7

arch/arm/mach-omap2/irq.c

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ 
#define INTC_MIR_CLEAR0		0x0088

#define INTC_MIR_SET0		0x008c

#define INTC_PENDING_IRQ0	0x0098

#define INTC_ILR0		0x0100

/* Number of IRQ state bits in each MIR register */

#define IRQ_BITS_PER_REG	32