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Commit 33a93aa4 authored by Anup Patel's avatar Anup Patel Committed by Florian Fainelli
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arm64: dts: Add L2-cache DT node for NS2 



Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.

Signed-off-by: default avatarAnup Patel <anup.patel@broadcom.com>
Reviewed-by: default avatarSandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: default avatarRay Jui <rjui@broadcom.com>
Reviewed-by: default avatarScott Branden <sbranden@broadcom.com>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 8005c49d

arch/arm64/boot/dts/broadcom/ns2.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
			reg = <0 0>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@1 {
@@ -58,6 +59,7 @@ 
			reg = <0 1>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@2 {
@@ -66,6 +68,7 @@ 
			reg = <0 2>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		cpu@3 {
@@ -74,6 +77,11 @@ 
			reg = <0 3>;

			enable-method = "spin-table";

			cpu-release-addr = <0 0x84b00000>;

			next-level-cache = <&CLUSTER0_L2>;

		};



		CLUSTER0_L2: l2-cache@000 {

			compatible = "cache";

		};

	};