Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 33466d93 authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: Prevent send BD corruption 



On rare occasions, send BD corruptions can occur.  This patch
fixes the problem by increasing the L1 entry threshold to 4
milliseconds.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent df259d8c

drivers/net/tg3.c

+7 −0
Original line number Diff line number Diff line
@@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		tw32(TG3_CPMU_HST_ACC, val);

	}



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {

		val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;

		val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |

		       PCIE_PWR_MGMT_L1_THRESH_4MS;

		tw32(PCIE_PWR_MGMT_THRESH, val);

	}



	/* This works around an issue with Athlon chipsets on

	 * B3 tigon3 silicon.  This bit has no effect on any

	 * other revision.  But do not set this on PCI Express

drivers/net/tg3.h

+2 −0
Original line number Diff line number Diff line
@@ -1697,6 +1697,8 @@ 


#define PCIE_PWR_MGMT_THRESH		0x00007d28

#define PCIE_PWR_MGMT_L1_THRESH_MSK	 0x0000ff00

#define PCIE_PWR_MGMT_L1_THRESH_4MS	 0x0000ff00

#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN	 0x01000000





/* OTP bit definitions */