Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 33057692 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM fixes from Russell King:
 "Not much here, just a couple minor/cosmetic fixes and a patch for the
  decompressor which fixes problems with modern GCC and CPUs."

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7583/1: decompressor: Enable unaligned memory access for v6 and above
  ARM: 7572/1: proc-v6.S: fix comment
  ARM: 7570/1: quiet down the non make -s output
parents 87726c33 5010192d

arch/arm/boot/compressed/head.S

+13 −1
Original line number Diff line number Diff line
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
		mov	pc, lr

ENDPROC(__setup_mmu)



@ Enable unaligned access on v6, to allow better code generation

@ for the decompressor C code:

__armv6_mmu_cache_on:

		mrc	p15, 0, r0, c1, c0, 0	@ read SCTLR

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

		mcr	p15, 0, r0, c1, c0, 0	@ write SCTLR

		b	__armv4_mmu_cache_on



__arm926ejs_mmu_cache_on:

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

		mov	r0, #4			@ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on: 
		bic	r0, r0, #1 << 28	@ clear SCTLR.TRE

		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement

		orr	r0, r0, #0x003c		@ write buffer

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

						@ (needed for ARM1176)

#ifdef CONFIG_MMU

#ifdef CONFIG_CPU_ENDIAN_BE8

		orr	r0, r0, #1 << 25	@ big-endian page tables
@@ -914,7 +926,7 @@ proc_types: 


		.word	0x0007b000		@ ARMv6

		.word	0x000ff000

		W(b)	__armv4_mmu_cache_on

		W(b)	__armv6_mmu_cache_on

		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush

arch/arm/mm/proc-v6.S

+1 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area) 
	mov	pc, lr



/*

 *	cpu_arm926_switch_mm(pgd_phys, tsk)

 *	cpu_v6_switch_mm(pgd_phys, tsk)

 *

 *	Set the translation table base pointer to be pgd_phys

 *