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Commit 32ee5c3d authored by Tony Lijo Jose's avatar Tony Lijo Jose Committed by Gerrit - the friendly Code Review server
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msm: camera: csiphy: Initialize cphy1.0 clock mask 



Add entries of 2phase clock lane bit mask and 2phase combo mode clock
lane bit mask while csiphy_reg initialization.Secure use case cp
regmask values will be calculated wrongly, if these values are not
initialized to correct values.

Change-Id: I1c4bd298275bed34981f75ff1cb43adf7d8e7951
Signed-off-by: default avatarTony Lijo Jose <tjose@codeaurora.org>
parent e2a199f7

drivers/media/platform/msm/camera_v3/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h

+3 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -23,6 +23,8 @@ struct csiphy_reg_parms_t csiphy_v1_0 = { 
	.csiphy_reset_array_size = 5,

	.csiphy_2ph_config_array_size = 14,

	.csiphy_3ph_config_array_size = 19,

	.csiphy_2ph_clock_lane = 0x1,

	.csiphy_2ph_combo_ck_ln = 0x10,

};



struct csiphy_reg_t csiphy_common_reg_1_0[] = {