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Commit 32e1d0a0 authored by Suresh Siddha's avatar Suresh Siddha Committed by Ingo Molnar
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x64, x2apic/intr-remap: cpuid bits for x2apic feature 



cpuid feature for x2apic.

Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
Cc: akpm@linux-foundation.org
Cc: arjan@linux.intel.com
Cc: andi@firstfloor.org
Cc: ebiederm@xmission.com
Cc: jbarnes@virtuousgeek.org
Cc: steiner@sgi.com
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 1b374e4d

arch/x86/kernel/cpu/feature_names.c

+1 −1
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ const char * const x86_cap_flags[NCAPINTS*32] = { 
	/* Intel-defined (#2) */

	"pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",

	"tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,

	NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",

	NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt",

	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



	/* VIA/Cyrix/Centaur-defined */

include/asm-x86/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ 
#define X86_FEATURE_CX16	(4*32+13) /* CMPXCHG16B */

#define X86_FEATURE_XTPR	(4*32+14) /* Send Task Priority Messages */

#define X86_FEATURE_DCA		(4*32+18) /* Direct Cache Access */

#define X86_FEATURE_X2APIC	(4*32+21) /* x2APIC */



/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */

#define X86_FEATURE_XSTORE	(5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -188,6 +189,7 @@ extern const char * const x86_power_flags[32]; 
#define cpu_has_gbpages		boot_cpu_has(X86_FEATURE_GBPAGES)

#define cpu_has_arch_perfmon	boot_cpu_has(X86_FEATURE_ARCH_PERFMON)

#define cpu_has_pat		boot_cpu_has(X86_FEATURE_PAT)

#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)



#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)

# define cpu_has_invlpg		1