Loading Documentation/devicetree/bindings/arm/coresight.txt +216 −6 Original line number Diff line number Diff line * CoreSight Components: CoreSight components are compliant with the ARM CoreSight architecture specification and can be connected in various topologies to suit a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. specification and can be connected in various topologies to suite a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. Required properties: - compatible : name of the component used for driver matching, should be one of the following: "arm,coresight-tmc" for coresight tmc-etr or tmc-etf device, "arm,coresight-tpiu" for coresight tpiu device, "qcom,coresight-replicator" for coresight replicator device, "arm,coresight-funnel" for coresight funnel devices, "qcom,coresight-tpda" for coresight tpda device, "qcom,coresight-tpdm" for coresight tpdm device, "qcom,coresight-dbgui" for coresight dbgui device "arm,coresight-stm" for coresight stm trace device, "arm,coresight-etm" for coresight etm trace devices, "arm,coresight-etmv4" for coresight etmv4 trace devices, "qcom,coresight-csr" for coresight csr device, "arm,coresight-cti" for coresight cti devices, "qcom,coresight-hwevent" for coresight hardware event devices "arm,coresight-fuse" for coresight fuse v1 device, "arm,coresight-fuse-v2" for coresight fuse v2 device, "arm,coresight-fuse-v3" for coresight fuse v3 device, "qcom,coresight-remote-etm" for coresight remote processor etm trace device, "qcom,coresight-qpdi" for coresight qpdi device - reg : physical base address and length of the register set(s) of the component. Not required for the following compatible string: - "qcom,coresight-remote-etm" - reg-names : names corresponding to each reg property value. Not required for the following compatible string: - "qcom,coresight-remote-etm" The reg-names that need to be used with corresponding compatible string for a coresight device are: - for coresight tmc-etr or tmc-etf device: compatible : should be "arm,coresight-tmc" reg-names : should be: "tmc-base" - physical base address of tmc configuration registers "bam-base" - physical base address of tmc-etr bam registers - for coresight tpiu device: compatible : should be "arm,coresight-tpiu" reg-names : should be: "tpiu-base" - physical base address of tpiu registers - for coresight replicator device compatible : should be "qcom,coresight-replicator" reg-names : should be: "replicator-base" - physical base address of replicator registers - for coresight funnel devices compatible : should be "arm,coresight-funnel" reg-names : should be: "funnel-base" - physical base address of funnel registers - for coresight tpda trace device compatible : should be "qcom,coresight-tpda" reg-names : should be: "tpda-base" - physical base address of tpda registers - for coresight tpdm trace device compatible : should be "qcom,coresight-tpdm" reg-names : should be: "tpdm-base" - physical base address of tpdm registers - for coresight dbgui device: compatible : should be "qcom,coresight-dbgui" reg-names : should be: "dbgui-base" - physical base address of dbgui registers - for coresight stm trace device compatible : should be "arm,coresight-stm" reg-names : should be: "stm-base" - physical base address of stm configuration registers "stm-data-base" - physical base address of stm data registers - for coresight etm trace devices compatible : should be "arm,coresight-etm" reg-names : should be: "etm-base" - physical base address of etm registers - for coresight etmv4 trace devices compatible : should be "arm,coresight-etmv4" reg-names : should be: "etm-base" - physical base address of etmv4 registers - for coresight csr device: compatible : should be "qcom,coresight-csr" reg-names : should be: "csr-base" - physical base address of csr registers - for coresight cti devices: compatible : should be "arm,coresight-cti" reg-names : should be: "cti<num>-base" - physical base address of cti registers - for coresight hardware event devices: compatible : should be "qcom,coresight-hwevent" reg-names : should be: "<ss-mux>" - physical base address of hardware event mux control registers where <ss-mux> is subsystem mux it represents - for coresight fuse device: compatible : should be "arm,coresight-fuse" reg-names : should be: "fuse-base" - physical base address of fuse registers "nidnt-fuse-base" - physical base address of nidnt fuse registers "qpdi-fuse-base" - physical base address of qpdi fuse registers - for coresight qpdi device: compatible : should be "qcom,coresight-qpdi" reg-names : should be: "qpdi-base" - physical base address of qpdi registers - coresight-id : unique integer identifier for the component - coresight-name : unique descriptive name of the component - coresight-nr-inports : number of input ports on the component Optional properties: - coresight-outports : list of output port numbers of this component - coresight-child-list : list of phandles pointing to the children of this component - coresight-child-ports : list of input port numbers of the children - coresight-default-sink : represents the default compile time CoreSight sink - coresight-ctis : list of ctis that this component interacts with - qcom,cti-save : boolean, indicating cti context needs to be saved and restored - qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti registers to be saved and restored - qcom,cti-gpio-trigin : cti trigger input driven by gpio - qcom,cti-gpio-trigout : cti trigger output sent to gpio - qcom,pc-save : program counter save implemented - qcom,blk-size : block size for tmc-etr to usb transfers - qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer - qcom,round-robin : indicates if per core etms are allowed round-robin access by the funnel - qcom,write-64bit : only 64bit data writes supported by stm - qcom,data-barrier : barrier required for every stm data write to channel space - <supply-name>-supply: phandle to the regulator device tree node. The required <supply-name> is "vdd" for SD card and "vdd-io" for SD I/O supply. Used for tpiu component - qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should be specified in pairs (min, max) with units being uV. Here <supply> can be "vdd" for SD card vdd supply or "vdd-io" for SD I/O vdd supply. - qcom,<supply>-current-level : specifies current load levels for vdd supply. Should be specified in pairs (lpm, hpm) with units being uA. Here <supply> can be "vdd" for SD card vdd supply or "vdd-io" for SD I/O vdd supply. - qcom,hwevent-clks : list of clocks required by hardware event driver - qcom,hwevent-regs : list of regulators required by hardware event driver - qcom,byte-cntr-absent : specifies if the byte counter feature is absent on the device. Only relevant in case of tmc-etr device. - interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is spi/ppi, b is the interrupt number and c is the mask, - interrupt-names : a list of strings that map in order to the list of interrupts specified in the 'interrupts' property. - qcom,sg-enable : indicates whether scatter gather feature is supported for TMC ETR configuration. - qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped. Used for TMC component - qcom,nidntsw : boolean, indicating NIDnT software debug or trace support present. Used for tpiu component - qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present. Used for tpiu component qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of these may specified for tpiu component - qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used for tpiu component - qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used for tpiu component - qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used for tpiu component - qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used for tpiu component - nidnt-gpio : specifies gpio for NIDnT hardware detection - nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection - pinctrl-names : names corresponding to the numbered pinctrl. The allowed names are subset of the following: cti-trigin-pctrl, cti-trigout-pctrl. Used for cti component - pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt". - qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled for the ETM whose CPU is being powered down. The port state is restored when CPU is powered up. Used for funnel component. - qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before powering down CPU. Used for TMC component. - qcom,bc-elem-size : specifies the BC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, bc element size). - qcom,tc-elem-size : specifies the TC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, tc element size). - qcom,dsb-elem-size : specifies the DSB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, dsb element size). - qcom,cmb-elem-size : specifies the CMB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, cmb element size). - qcom,clk-enable: specifies whether additional clock bit needs to be set for M4M TPDM. - qcom,tpda-atid : specifies the ATID for TPDA. - qcom,inst-id : QMI instance id for remote ETMs. - qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be set in ETM stall control register. - coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true - coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device - qcom,dbgui-addr-offset : indicates the offset of dbgui address registers - qcom,dbgui-data-offset : indicates the offset of dbgui data registers - qcom,dbgui-size : indicates the size of dbgui address and data registers - qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver - qcom,cpuss-debug-cgc: debug clock gating phandle for etm reg : the clock gating register for each cluster cluster : indicate the cluster number coresight-outports, coresight-child-list and coresight-child-ports lists will be of the same length and will have a one to one correspondence among the elements at the same list index. coresight-default-sink must be specified for one of the sink devices that is intended to be made the default sink. Other sink devices must not have this specified. Not specifying this property on any of the sinks is invalid. * Required properties for all components *except* non-configurable replicators: Loading Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt 0 → 100644 +43 −0 Original line number Diff line number Diff line * Qualcomm Application CPU clock driver clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls the cpu rate. RCGs support selecting one of several clock inputs, as well as a configurable divider. This hw is different than normal rcgs in that it may optionally have a register which encodes the maximum rate supported by hw. Required properties: - compatible: "qcom,clock-a53-8916", "qcom,clock-a7-9650", "qcom,clock-a7-mdm9607", "qcom,clock-a7-sdx20" - reg: pairs of physical address and region size - reg-names: "rcg-base" is expected - clock-names: list of names of clock inputs - qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping. Format: <freq uV> This represents the max frequency possible for each possible power configuration for a CPU that's binned as speed bin X, speed bin revision Z. Speed bin values can be between [0-7] and the version can be between [0-3]. - cpu-vdd-supply: regulator phandle for cpu power domain. Optional properties: - reg-names: "efuse", "efuse1" - qcom,safe-freq: Frequency in HZ When switching rates from A to B, the mux div clock will instead switch from A -> safe_freq -> B. - qcom,enable-opp: This will allow to register the cpu clock with OPP framework. Example: qcom,acpuclk@f9011050 { compatible = "qcom,clock-a7-8226"; reg = <0xf9011050 0x8>; reg-names = "rcg_base"; cpu-vdd-supply = <&apc_vreg_corner>; clock-names = "clk-4", "clk-5"; qcom,speed0-bin-v0 = <384000000 1150000>, <600000000 1200000>; }; Documentation/devicetree/bindings/arm/msm/clock-controller.txt +5 −0 Original line number Diff line number Diff line Loading @@ -12,8 +12,10 @@ the compatible string to indicate the revision. Required properties: - compatible: Must be one of following, "qcom,gcc-8953" "qcom,gcc-8909" "qcom,gcc-sdm632" "qcom,cc-debug-8953" "qcom,cc-debug-8909" "qcom,cc-debug-sdm632" "qcom,gcc-mdss-8953" "qcom,gcc-mdss-sdm632" Loading @@ -28,6 +30,8 @@ Required properties: "qcom,gcc-8920" "qcom,gcc-spm-8952" "qcom,gcc-spm-8937" "qcom,rpmcc-8909" "qcom,rpmcc-8909-pm660" "qcom,cc-debug-8952" "qcom,cc-debug-8953" "qcom,cc-debug-8937" Loading @@ -36,6 +40,7 @@ Required properties: "qcom,cc-debug-8920" "qcom,gcc-mdss-8953" "qcom,gcc-mdss-8952" "qcom,gcc-mdss-8909" "qcom,gcc-mdss-8937" "qcom,gcc-mdss-8917" "qcom,gcc-mdss-8940" Loading Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt 0 → 100644 +49 −0 Original line number Diff line number Diff line * MSM Sleep status MSM Sleep status device is used to check the power collapsed status of a offlined core. The core that initiates the hotplug would wait on the sleep status device before CPU_DEAD notifications are sent out. Some hardware devices require that the offlined core is power collapsed before turning off the resources that are used by the offlined core. The required properties of core sleep status node are: - compatible: qcom,cpu-sleep-status The required properties of sleep status node are: - reg: physical address of the sleep status register for the cpus - qcom,cpu-sleep-status-mask - The bit mask within the status register that indicates the Core's sleep state. Example: qcom,cpu-sleep-status { compatible = "qcom,cpu-sleep-status"; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo"; qcom,sleep-status = <&cpu0_slp_sts>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "qcom,kryo"; qcom,sleep-status = <&cpu1_slp_sts>; }; }; cpu0_slp_sts: cpu-sleep-status@9981058 { reg = <0x9981058 0x100>; qcom,sleep-status-mask = <0xc00000>; }; cpu1_slp_sts: cpu-sleep-status@9991058 { reg = <0x9991058 0x100>; qcom,sleep-status-mask = <0xc00000>; } Documentation/devicetree/bindings/arm/msm/glink_bgcom_xprt.txt 0 → 100644 +33 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. G-link bgcom Transport Required properties: -compatible : should be "qcom,glink-bgcom-xprt". -label : the name of the subsystem this link connects to. Optional properties: -qcom,qos-config: Reference to the qos configuration elements.It depends on ramp-time. -qcom,ramp-time: Worst case time in microseconds to transition to this power state. Power states are numbered by array index position. Example: qcom,glink-bgcom-xprt-bg { compatible = "qcom,glink-bgcom-xprt"; label = "bg"; qcom,qos-config = <&glink_qos_bg>; qcom,ramp-time = <0x10>, <0x20>, <0x30>, <0x40>; }; glink_qos_bg: qcom,glink-qos-config-bg { compatible = "qcom,glink-qos-config"; qcom,flow-info = <0x80 0x0>, <0x70 0x1>, <0x60 0x2>, <0x50 0x3>; qcom,mtu-size = <0x800>; qcom,tput-stats-cycle = <0xa>; }; Loading
Documentation/devicetree/bindings/arm/coresight.txt +216 −6 Original line number Diff line number Diff line * CoreSight Components: CoreSight components are compliant with the ARM CoreSight architecture specification and can be connected in various topologies to suit a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. specification and can be connected in various topologies to suite a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. Required properties: - compatible : name of the component used for driver matching, should be one of the following: "arm,coresight-tmc" for coresight tmc-etr or tmc-etf device, "arm,coresight-tpiu" for coresight tpiu device, "qcom,coresight-replicator" for coresight replicator device, "arm,coresight-funnel" for coresight funnel devices, "qcom,coresight-tpda" for coresight tpda device, "qcom,coresight-tpdm" for coresight tpdm device, "qcom,coresight-dbgui" for coresight dbgui device "arm,coresight-stm" for coresight stm trace device, "arm,coresight-etm" for coresight etm trace devices, "arm,coresight-etmv4" for coresight etmv4 trace devices, "qcom,coresight-csr" for coresight csr device, "arm,coresight-cti" for coresight cti devices, "qcom,coresight-hwevent" for coresight hardware event devices "arm,coresight-fuse" for coresight fuse v1 device, "arm,coresight-fuse-v2" for coresight fuse v2 device, "arm,coresight-fuse-v3" for coresight fuse v3 device, "qcom,coresight-remote-etm" for coresight remote processor etm trace device, "qcom,coresight-qpdi" for coresight qpdi device - reg : physical base address and length of the register set(s) of the component. Not required for the following compatible string: - "qcom,coresight-remote-etm" - reg-names : names corresponding to each reg property value. Not required for the following compatible string: - "qcom,coresight-remote-etm" The reg-names that need to be used with corresponding compatible string for a coresight device are: - for coresight tmc-etr or tmc-etf device: compatible : should be "arm,coresight-tmc" reg-names : should be: "tmc-base" - physical base address of tmc configuration registers "bam-base" - physical base address of tmc-etr bam registers - for coresight tpiu device: compatible : should be "arm,coresight-tpiu" reg-names : should be: "tpiu-base" - physical base address of tpiu registers - for coresight replicator device compatible : should be "qcom,coresight-replicator" reg-names : should be: "replicator-base" - physical base address of replicator registers - for coresight funnel devices compatible : should be "arm,coresight-funnel" reg-names : should be: "funnel-base" - physical base address of funnel registers - for coresight tpda trace device compatible : should be "qcom,coresight-tpda" reg-names : should be: "tpda-base" - physical base address of tpda registers - for coresight tpdm trace device compatible : should be "qcom,coresight-tpdm" reg-names : should be: "tpdm-base" - physical base address of tpdm registers - for coresight dbgui device: compatible : should be "qcom,coresight-dbgui" reg-names : should be: "dbgui-base" - physical base address of dbgui registers - for coresight stm trace device compatible : should be "arm,coresight-stm" reg-names : should be: "stm-base" - physical base address of stm configuration registers "stm-data-base" - physical base address of stm data registers - for coresight etm trace devices compatible : should be "arm,coresight-etm" reg-names : should be: "etm-base" - physical base address of etm registers - for coresight etmv4 trace devices compatible : should be "arm,coresight-etmv4" reg-names : should be: "etm-base" - physical base address of etmv4 registers - for coresight csr device: compatible : should be "qcom,coresight-csr" reg-names : should be: "csr-base" - physical base address of csr registers - for coresight cti devices: compatible : should be "arm,coresight-cti" reg-names : should be: "cti<num>-base" - physical base address of cti registers - for coresight hardware event devices: compatible : should be "qcom,coresight-hwevent" reg-names : should be: "<ss-mux>" - physical base address of hardware event mux control registers where <ss-mux> is subsystem mux it represents - for coresight fuse device: compatible : should be "arm,coresight-fuse" reg-names : should be: "fuse-base" - physical base address of fuse registers "nidnt-fuse-base" - physical base address of nidnt fuse registers "qpdi-fuse-base" - physical base address of qpdi fuse registers - for coresight qpdi device: compatible : should be "qcom,coresight-qpdi" reg-names : should be: "qpdi-base" - physical base address of qpdi registers - coresight-id : unique integer identifier for the component - coresight-name : unique descriptive name of the component - coresight-nr-inports : number of input ports on the component Optional properties: - coresight-outports : list of output port numbers of this component - coresight-child-list : list of phandles pointing to the children of this component - coresight-child-ports : list of input port numbers of the children - coresight-default-sink : represents the default compile time CoreSight sink - coresight-ctis : list of ctis that this component interacts with - qcom,cti-save : boolean, indicating cti context needs to be saved and restored - qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti registers to be saved and restored - qcom,cti-gpio-trigin : cti trigger input driven by gpio - qcom,cti-gpio-trigout : cti trigger output sent to gpio - qcom,pc-save : program counter save implemented - qcom,blk-size : block size for tmc-etr to usb transfers - qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer - qcom,round-robin : indicates if per core etms are allowed round-robin access by the funnel - qcom,write-64bit : only 64bit data writes supported by stm - qcom,data-barrier : barrier required for every stm data write to channel space - <supply-name>-supply: phandle to the regulator device tree node. The required <supply-name> is "vdd" for SD card and "vdd-io" for SD I/O supply. Used for tpiu component - qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should be specified in pairs (min, max) with units being uV. Here <supply> can be "vdd" for SD card vdd supply or "vdd-io" for SD I/O vdd supply. - qcom,<supply>-current-level : specifies current load levels for vdd supply. Should be specified in pairs (lpm, hpm) with units being uA. Here <supply> can be "vdd" for SD card vdd supply or "vdd-io" for SD I/O vdd supply. - qcom,hwevent-clks : list of clocks required by hardware event driver - qcom,hwevent-regs : list of regulators required by hardware event driver - qcom,byte-cntr-absent : specifies if the byte counter feature is absent on the device. Only relevant in case of tmc-etr device. - interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is spi/ppi, b is the interrupt number and c is the mask, - interrupt-names : a list of strings that map in order to the list of interrupts specified in the 'interrupts' property. - qcom,sg-enable : indicates whether scatter gather feature is supported for TMC ETR configuration. - qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped. Used for TMC component - qcom,nidntsw : boolean, indicating NIDnT software debug or trace support present. Used for tpiu component - qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present. Used for tpiu component qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of these may specified for tpiu component - qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used for tpiu component - qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used for tpiu component - qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used for tpiu component - qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used for tpiu component - nidnt-gpio : specifies gpio for NIDnT hardware detection - nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection - pinctrl-names : names corresponding to the numbered pinctrl. The allowed names are subset of the following: cti-trigin-pctrl, cti-trigout-pctrl. Used for cti component - pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt". - qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled for the ETM whose CPU is being powered down. The port state is restored when CPU is powered up. Used for funnel component. - qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before powering down CPU. Used for TMC component. - qcom,bc-elem-size : specifies the BC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, bc element size). - qcom,tc-elem-size : specifies the TC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, tc element size). - qcom,dsb-elem-size : specifies the DSB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, dsb element size). - qcom,cmb-elem-size : specifies the CMB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, cmb element size). - qcom,clk-enable: specifies whether additional clock bit needs to be set for M4M TPDM. - qcom,tpda-atid : specifies the ATID for TPDA. - qcom,inst-id : QMI instance id for remote ETMs. - qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be set in ETM stall control register. - coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true - coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device - qcom,dbgui-addr-offset : indicates the offset of dbgui address registers - qcom,dbgui-data-offset : indicates the offset of dbgui data registers - qcom,dbgui-size : indicates the size of dbgui address and data registers - qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver - qcom,cpuss-debug-cgc: debug clock gating phandle for etm reg : the clock gating register for each cluster cluster : indicate the cluster number coresight-outports, coresight-child-list and coresight-child-ports lists will be of the same length and will have a one to one correspondence among the elements at the same list index. coresight-default-sink must be specified for one of the sink devices that is intended to be made the default sink. Other sink devices must not have this specified. Not specifying this property on any of the sinks is invalid. * Required properties for all components *except* non-configurable replicators: Loading
Documentation/devicetree/bindings/arm/msm/acpuclock/clock-a7.txt 0 → 100644 +43 −0 Original line number Diff line number Diff line * Qualcomm Application CPU clock driver clock-a7 is the driver for the Root Clock Generator (rcg) hw which controls the cpu rate. RCGs support selecting one of several clock inputs, as well as a configurable divider. This hw is different than normal rcgs in that it may optionally have a register which encodes the maximum rate supported by hw. Required properties: - compatible: "qcom,clock-a53-8916", "qcom,clock-a7-9650", "qcom,clock-a7-mdm9607", "qcom,clock-a7-sdx20" - reg: pairs of physical address and region size - reg-names: "rcg-base" is expected - clock-names: list of names of clock inputs - qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping. Format: <freq uV> This represents the max frequency possible for each possible power configuration for a CPU that's binned as speed bin X, speed bin revision Z. Speed bin values can be between [0-7] and the version can be between [0-3]. - cpu-vdd-supply: regulator phandle for cpu power domain. Optional properties: - reg-names: "efuse", "efuse1" - qcom,safe-freq: Frequency in HZ When switching rates from A to B, the mux div clock will instead switch from A -> safe_freq -> B. - qcom,enable-opp: This will allow to register the cpu clock with OPP framework. Example: qcom,acpuclk@f9011050 { compatible = "qcom,clock-a7-8226"; reg = <0xf9011050 0x8>; reg-names = "rcg_base"; cpu-vdd-supply = <&apc_vreg_corner>; clock-names = "clk-4", "clk-5"; qcom,speed0-bin-v0 = <384000000 1150000>, <600000000 1200000>; };
Documentation/devicetree/bindings/arm/msm/clock-controller.txt +5 −0 Original line number Diff line number Diff line Loading @@ -12,8 +12,10 @@ the compatible string to indicate the revision. Required properties: - compatible: Must be one of following, "qcom,gcc-8953" "qcom,gcc-8909" "qcom,gcc-sdm632" "qcom,cc-debug-8953" "qcom,cc-debug-8909" "qcom,cc-debug-sdm632" "qcom,gcc-mdss-8953" "qcom,gcc-mdss-sdm632" Loading @@ -28,6 +30,8 @@ Required properties: "qcom,gcc-8920" "qcom,gcc-spm-8952" "qcom,gcc-spm-8937" "qcom,rpmcc-8909" "qcom,rpmcc-8909-pm660" "qcom,cc-debug-8952" "qcom,cc-debug-8953" "qcom,cc-debug-8937" Loading @@ -36,6 +40,7 @@ Required properties: "qcom,cc-debug-8920" "qcom,gcc-mdss-8953" "qcom,gcc-mdss-8952" "qcom,gcc-mdss-8909" "qcom,gcc-mdss-8937" "qcom,gcc-mdss-8917" "qcom,gcc-mdss-8940" Loading
Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt 0 → 100644 +49 −0 Original line number Diff line number Diff line * MSM Sleep status MSM Sleep status device is used to check the power collapsed status of a offlined core. The core that initiates the hotplug would wait on the sleep status device before CPU_DEAD notifications are sent out. Some hardware devices require that the offlined core is power collapsed before turning off the resources that are used by the offlined core. The required properties of core sleep status node are: - compatible: qcom,cpu-sleep-status The required properties of sleep status node are: - reg: physical address of the sleep status register for the cpus - qcom,cpu-sleep-status-mask - The bit mask within the status register that indicates the Core's sleep state. Example: qcom,cpu-sleep-status { compatible = "qcom,cpu-sleep-status"; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo"; qcom,sleep-status = <&cpu0_slp_sts>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "qcom,kryo"; qcom,sleep-status = <&cpu1_slp_sts>; }; }; cpu0_slp_sts: cpu-sleep-status@9981058 { reg = <0x9981058 0x100>; qcom,sleep-status-mask = <0xc00000>; }; cpu1_slp_sts: cpu-sleep-status@9991058 { reg = <0x9991058 0x100>; qcom,sleep-status-mask = <0xc00000>; }
Documentation/devicetree/bindings/arm/msm/glink_bgcom_xprt.txt 0 → 100644 +33 −0 Original line number Diff line number Diff line Qualcomm Technologies, Inc. G-link bgcom Transport Required properties: -compatible : should be "qcom,glink-bgcom-xprt". -label : the name of the subsystem this link connects to. Optional properties: -qcom,qos-config: Reference to the qos configuration elements.It depends on ramp-time. -qcom,ramp-time: Worst case time in microseconds to transition to this power state. Power states are numbered by array index position. Example: qcom,glink-bgcom-xprt-bg { compatible = "qcom,glink-bgcom-xprt"; label = "bg"; qcom,qos-config = <&glink_qos_bg>; qcom,ramp-time = <0x10>, <0x20>, <0x30>, <0x40>; }; glink_qos_bg: qcom,glink-qos-config-bg { compatible = "qcom,glink-qos-config"; qcom,flow-info = <0x80 0x0>, <0x70 0x1>, <0x60 0x2>, <0x50 0x3>; qcom,mtu-size = <0x800>; qcom,tput-stats-cycle = <0xa>; };
