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Commit 32080af7 authored by Jarkko Nikula's avatar Jarkko Nikula Committed by Mark Brown
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ASoC: OMAP: Fix setup of XCCR and RCCR registers in McBSP DAI 



Commit ca6e2ce0 is setting up few XCCR and
RCCR bits for I2S and DPS_A formats. Part of the bits are already set
for all formats and I believe that XDISABLE and RDISABLE bits are
format independent.

As XCCR and RCCR are found only from OMAP2430 and OMAP34xx, I move setup
of XDISABLE and RDISABLE to where those cpu's are tested and remove format
dependent part for simplicity.

Signed-off-by: default avatarJarkko Nikula <jhnikula@gmail.com>
Acked-by: default avatarEero Nurkkala <ext-eero.nurkkala@nokia.com>
Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 9b300509

sound/soc/omap/omap-mcbsp.c

+2 −6
Original line number Diff line number Diff line
@@ -379,8 +379,8 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
		regs->xcr2	|= XFIG;

	}

	if (cpu_is_omap2430() || cpu_is_omap34xx()) {

		regs->xccr = DXENDLY(1) | XDMAEN;

		regs->rccr = RFULL_CYCLE | RDMAEN;

		regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;

		regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;

	}



	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -388,15 +388,11 @@ static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
		/* 1-bit data delay */

		regs->rcr2	|= RDATDLY(1);

		regs->xcr2	|= XDATDLY(1);

		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;

		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);

		break;

	case SND_SOC_DAIFMT_DSP_A:

		/* 1-bit data delay */

		regs->rcr2      |= RDATDLY(1);

		regs->xcr2      |= XDATDLY(1);

		regs->rccr	|= RFULL_CYCLE | RDMAEN | RDISABLE;

		regs->xccr	|= (DXENDLY(1) | XDMAEN | XDISABLE);

		/* Invert FS polarity configuration */

		temp_fmt ^= SND_SOC_DAIFMT_NB_IF;

		break;