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Commit 320787c7 authored by Paul Mackerras's avatar Paul Mackerras
Browse files

[POWERPC] Fix handling of unrecoverable SLB miss interrupts 



If an SLB miss interrupt happens while the RI bit of MSR is zero, we
can't just return, because RI being zero indicates that SRR0/SRR1
potentially had live values in them, and the process of taking an
interrupt overwrites them.

This should never happen, but if it does, we try to print a nice oops
message.  That doesn't work, however, because the code at unrecov_slb
assumes that the MMU has been turned on, but we call it with the MMU
off (and have done so since the SLB miss handler was rewritten to run
without turning the MMU on) -- except on iSeries, where everything runs
with the MMU on.

This fixes it by adding the necessary code to turn the MMU on if
necessary.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent ac7c5353

arch/powerpc/kernel/head_64.S

+17 −1
Original line number Diff line number Diff line
@@ -621,7 +621,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 
	mtlr	r10



	andi.	r10,r12,MSR_RI	/* check for unrecoverable exception */

	beq-	unrecov_slb

	beq-	2f



.machine	push

.machine	"power4"
@@ -643,6 +643,22 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) 
	rfid

	b	.	/* prevent speculative execution */



2:

#ifdef CONFIG_PPC_ISERIES

BEGIN_FW_FTR_SECTION

	b	unrecov_slb

END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)

#endif /* CONFIG_PPC_ISERIES */

	mfspr	r11,SPRN_SRR0

	clrrdi	r10,r13,32

	LOAD_HANDLER(r10,unrecov_slb)

	mtspr	SPRN_SRR0,r10

	mfmsr	r10

	ori	r10,r10,MSR_IR|MSR_DR|MSR_RI

	mtspr	SPRN_SRR1,r10

	rfid

	b	.



unrecov_slb:

	EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)

	DISABLE_INTS