Merge "ARM: dts: msm: Add memlat and L3 cache voter devices for sdm845" into msm-4.9

		qcom,target-dev = <&cpubw>;

	};

	memlat_cpu0: qcom,memlat-cpu0 {

		compatible = "qcom,devbw";

		governor = "powersave";

		qcom,src-dst-ports = <1 512>;

		qcom,active-only;

		qcom,bw-tbl =

			<  762 /*  200 MHz */ >,

			< 1144 /*  300 MHz */ >,

			< 1720 /*  451 MHz */ >,

			< 2086 /*  547 MHz */ >,

			< 2597 /*  681 MHz */ >,

			< 2929 /*  768 MHz */ >,

			< 3879 /* 1017 MHz */ >,

			< 4943 /* 1296 MHz */ >,

			< 5931 /* 1555 MHz */ >,

			< 6881 /* 1804 MHz */ >;

	};

	memlat_cpu4: qcom,memlat-cpu4 {

		compatible = "qcom,devbw";

		governor = "powersave";

		qcom,src-dst-ports = <1 512>;

		qcom,active-only;

		status = "ok";

		qcom,bw-tbl =

			<  762 /*  200 MHz */ >,

			< 1144 /*  300 MHz */ >,

			< 1720 /*  451 MHz */ >,

			< 2086 /*  547 MHz */ >,

			< 2597 /*  681 MHz */ >,

			< 2929 /*  768 MHz */ >,

			< 3879 /* 1017 MHz */ >,

			< 4943 /* 1296 MHz */ >,

			< 5931 /* 1555 MHz */ >,

			< 6881 /* 1804 MHz */ >;

	};

	devfreq_memlat_0: qcom,cpu0-memlat-mon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&memlat_cpu0>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			<  300000  762 >,

			<  748800 1720 >,

			<  979200 2929 >,

			< 1209600 3879 >,

			< 1516800 4943 >,

			< 1593600 5931 >;

	};

	devfreq_memlat_4: qcom,cpu4-memlat-mon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,target-dev = <&memlat_cpu4>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			<  300000  762 >,

			< 1036800 2929 >,

			< 1190400 3879 >,

			< 1574400 4943 >,

			< 1804800 5931 >,

			< 1958400 6881 >;

	};

	l3_cpu0: qcom,l3-cpu0 {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>;

		governor = "performance";

		freq-tbl-khz =

			< 300000 >,

			< 422400 >,

			< 499200 >,

			< 576000 >,

			< 652800 >,

			< 729600 >,

			< 806400 >,

			< 883200 >,

			< 960000 >;

	};

	l3_cpu4: qcom,l3-cpu4 {

		compatible = "devfreq-simple-dev";

		clock-names = "devfreq_clk";

		clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>;

		governor = "performance";

		freq-tbl-khz =

			< 300000 >,

			< 422400 >,

			< 499200 >,

			< 576000 >,

			< 652800 >,

			< 729600 >,

			< 806400 >,

			< 883200 >,

			< 960000 >;

	};

	devfreq_l3lat_0: qcom,cpu0-l3lat-mon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

		qcom,target-dev = <&l3_cpu0>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =

			<  300000 300000 >,

			<  748800 576000 >,

			<  979200 652800 >,

			< 1209600 806400 >,

			< 1516800 883200 >,

			< 1593600 960000 >;

	};

	devfreq_l3lat_4: qcom,cpu4-l3lat-mon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

		qcom,target-dev = <&l3_cpu4>;

		qcom,cachemiss-ev = <0x17>;

		qcom,core-dev-table =

			<  300000 300000 >,

			< 1036800 652800 >,

			< 1190400 806400 >,

			< 1574400 883200 >,

			< 1651200 960000 >;

	};

	clock_gcc: qcom,gcc@100000 {

		compatible = "qcom,gcc-sdm845";

		reg = <0x100000 0x1f0000>;