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Commit 3122e500 authored by Satyajit Desai's avatar Satyajit Desai
Browse files

ARM: dts: msm: Add coresight CTI devices for SDM845 



Add DDR and DLMM CTI devices for SDM845. The CTI devices on these
subsytesm can be used to input or output i.e. pass cross trigger
events from one hardware component to another. These can also be
used to generate SW events.

Change-Id: Ib114408bceec3aec46448b82597b122bfeadcc8b
Signed-off-by: default avatarSatyajit Desai <sadesai@codeaurora.org>
parent ca337de5

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+40 −4
Original line number Diff line number Diff line
@@ -1396,25 +1396,61 @@ 
		};

	};



	cti_ddr0: cti@69e1000 {

	cti0_ddr0: cti@69e1000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x69e1000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr0";

		coresight-name = "coresight-cti0-ddr0";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti_ddr1: cti@69e4000 {

	cti0_ddr1: cti@69e4000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x69e4000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti-ddr1";

		coresight-name = "coresight-cti0-ddr1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_ddr1: cti@69e5000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x69e5000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-ddr1";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti0_dlmm: cti@6c09000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c09000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti0-dlmm";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};



	cti1_dlmm: cti@6c0a000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b966>;

		reg = <0x6c0a000 0x1000>;

		reg-names = "cti-base";



		coresight-name = "coresight-cti1-dlmm";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";