Merge "ARM: dts: msm: add sdhc pinctrl drive types for SDM845" (3111a0a5) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-mtp.dtsi

+10 −1

Original line number	Diff line number	Diff line
		@@ -239,9 +239,18 @@
		qcom,vdd-io-voltage-level = <1808000 2960000>;
		qcom,vdd-io-current-level = <200 22000>;

		pinctrl-names = "active", "sleep";
		pinctrl-names = "active", "sleep", "ds_400KHz",
		"ds_50MHz", "ds_100MHz", "ds_200MHz";
		pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
		pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
		pinctrl-2 = <&sdc2_clk_ds_400KHz
		&sdc2_cmd_ds_400KHz &sdc2_data_ds_400KHz>;
		pinctrl-3 = <&sdc2_clk_ds_50MHz
		&sdc2_cmd_ds_50MHz &sdc2_data_ds_50MHz>;
		pinctrl-4 = <&sdc2_clk_ds_100MHz
		&sdc2_cmd_ds_100MHz &sdc2_data_ds_100MHz>;
		pinctrl-5 = <&sdc2_clk_ds_200MHz
		&sdc2_cmd_ds_200MHz &sdc2_data_ds_200MHz>;

		cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+96 −0

Original line number	Diff line number	Diff line
		@@ -142,6 +142,38 @@
		};
		};

		sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
		config {
		pins = "sdc2_clk";
		bias-disable; /* NO pull */
		drive-strength = <16>; /* 16 MA */
		};
		};

		sdc2_cmd_on: sdc2_cmd_on {
		config {
		pins = "sdc2_cmd";
		@@ -158,6 +190,38 @@
		};
		};

		sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
		config {
		pins = "sdc2_cmd";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_on: sdc2_data_on {
		config {
		pins = "sdc2_data";
		@@ -174,6 +238,38 @@
		};
		};

		sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
		config {
		pins = "sdc2_data";
		bias-pull-up; /* pull up */
		drive-strength = <10>; /* 10 MA */
		};
		};

		pcie0 {
		pcie0_clkreq_default: pcie0_clkreq_default {
		mux {

drivers/mmc/host/sdhci-msm.c

+57 −0

Original line number	Diff line number	Diff line
		@@ -1406,6 +1406,32 @@ static int sdhci_msm_setup_gpio(struct sdhci_msm_pltfm_data *pdata, bool enable)
		return ret;
		}

		static int sdhci_msm_config_pinctrl_drv_type(struct sdhci_msm_pltfm_data *pdata,
		unsigned int clock)
		{
		int ret = 0;

		if (clock > 150000000) {
		if (pdata->pctrl_data->pins_drv_type_200MHz)
		ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
		pdata->pctrl_data->pins_drv_type_200MHz);
		} else if (clock > 75000000) {
		if (pdata->pctrl_data->pins_drv_type_100MHz)
		ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
		pdata->pctrl_data->pins_drv_type_100MHz);
		} else if (clock > 400000) {
		if (pdata->pctrl_data->pins_drv_type_50MHz)
		ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
		pdata->pctrl_data->pins_drv_type_50MHz);
		} else {
		if (pdata->pctrl_data->pins_drv_type_400KHz)
		ret = pinctrl_select_state(pdata->pctrl_data->pctrl,
		pdata->pctrl_data->pins_drv_type_400KHz);
		}

		return ret;
		}

		static int sdhci_msm_setup_pinctrl(struct sdhci_msm_pltfm_data *pdata,
		bool enable)
		{
		@@ -1586,6 +1612,27 @@ static int sdhci_msm_parse_pinctrl_info(struct device *dev,
		dev_err(dev, "Could not get sleep pinstates, err:%d\n", ret);
		goto out;
		}

		pctrl_data->pins_drv_type_400KHz = pinctrl_lookup_state(
		pctrl_data->pctrl, "ds_400KHz");
		if (IS_ERR(pctrl_data->pins_drv_type_400KHz))
		dev_dbg(dev, "Could not get 400K pinstates, err:%d\n", ret);

		pctrl_data->pins_drv_type_50MHz = pinctrl_lookup_state(
		pctrl_data->pctrl, "ds_50MHz");
		if (IS_ERR(pctrl_data->pins_drv_type_50MHz))
		dev_dbg(dev, "Could not get 50M pinstates, err:%d\n", ret);

		pctrl_data->pins_drv_type_100MHz = pinctrl_lookup_state(
		pctrl_data->pctrl, "ds_100MHz");
		if (IS_ERR(pctrl_data->pins_drv_type_100MHz))
		dev_dbg(dev, "Could not get 100M pinstates, err:%d\n", ret);

		pctrl_data->pins_drv_type_200MHz = pinctrl_lookup_state(
		pctrl_data->pctrl, "ds_200MHz");
		if (IS_ERR(pctrl_data->pins_drv_type_200MHz))
		dev_dbg(dev, "Could not get 200M pinstates, err:%d\n", ret);

		pdata->pctrl_data = pctrl_data;
		out:
		return ret;
		@@ -3349,6 +3396,16 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
		}
		msm_host->clk_rate = sup_clock;
		host->clock = clock;

		/* Configure pinctrl drive type according to
		* current clock rate
		*/
		rc = sdhci_msm_config_pinctrl_drv_type(msm_host->pdata, clock);
		if (rc)
		pr_err("%s: %s: Failed to set pinctrl drive type for clock rate %u (%d)\n",
		mmc_hostname(host->mmc), __func__,
		clock, rc);

		/*
		* Update the bus vote in case of frequency change due to
		* clock scaling.

drivers/mmc/host/sdhci-msm.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -76,6 +76,10 @@ struct sdhci_pinctrl_data {
		struct pinctrl *pctrl;
		struct pinctrl_state *pins_active;
		struct pinctrl_state *pins_sleep;
		struct pinctrl_state *pins_drv_type_400KHz;
		struct pinctrl_state *pins_drv_type_50MHz;
		struct pinctrl_state *pins_drv_type_100MHz;
		struct pinctrl_state *pins_drv_type_200MHz;
		};

		struct sdhci_msm_bus_voting_data {