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Commit 30ef898c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  i915: Add GEM ioctl to get available aperture size.
  drm/radeon: fixup further bus mastering confusion.
  build fix: CONFIG_DRM_I915=y && CONFIG_ACPI=n
parents 45beca08 5a125c3c

drivers/gpu/drm/i915/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -3,13 +3,14 @@ 
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.



ccflags-y := -Iinclude/drm

i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_opregion.o \

i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \

          i915_suspend.o \

	  i915_gem.o \

	  i915_gem_debug.o \

	  i915_gem_proc.o \

	  i915_gem_tiling.o



i915-$(CONFIG_ACPI)	+= i915_opregion.o

i915-$(CONFIG_COMPAT)   += i915_ioc32.o



obj-$(CONFIG_DRM_I915)  += i915.o

drivers/gpu/drm/i915/i915_dma.c

+1 −0
Original line number Diff line number Diff line
@@ -960,6 +960,7 @@ struct drm_ioctl_desc i915_ioctls[] = { 
	DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),

	DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),

};



int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);

drivers/gpu/drm/i915/i915_drv.h

+9 −0
Original line number Diff line number Diff line
@@ -502,6 +502,8 @@ int i915_gem_set_tiling(struct drm_device *dev, void *data, 
			struct drm_file *file_priv);

int i915_gem_get_tiling(struct drm_device *dev, void *data,

			struct drm_file *file_priv);

int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,

				struct drm_file *file_priv);

void i915_gem_load(struct drm_device *dev);

int i915_gem_proc_init(struct drm_minor *minor);

void i915_gem_proc_cleanup(struct drm_minor *minor);
@@ -539,11 +541,18 @@ extern int i915_restore_state(struct drm_device *dev); 
extern int i915_save_state(struct drm_device *dev);

extern int i915_restore_state(struct drm_device *dev);



#ifdef CONFIG_ACPI

/* i915_opregion.c */

extern int intel_opregion_init(struct drm_device *dev);

extern void intel_opregion_free(struct drm_device *dev);

extern void opregion_asle_intr(struct drm_device *dev);

extern void opregion_enable_asle(struct drm_device *dev);

#else

static inline int intel_opregion_init(struct drm_device *dev) { return 0; }

static inline void intel_opregion_free(struct drm_device *dev) { return; }

static inline void opregion_asle_intr(struct drm_device *dev) { return; }

static inline void opregion_enable_asle(struct drm_device *dev) { return; }

#endif



/**

 * Lock test for when it's just for synchronization of ring access.

drivers/gpu/drm/i915/i915_gem.c

+22 −0
Original line number Diff line number Diff line
@@ -79,6 +79,28 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data, 
	return 0;

}



int

i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,

			    struct drm_file *file_priv)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	struct drm_i915_gem_get_aperture *args = data;

	struct drm_i915_gem_object *obj_priv;



	if (!(dev->driver->driver_features & DRIVER_GEM))

		return -ENODEV;



	args->aper_size = dev->gtt_total;

	args->aper_available_size = args->aper_size;



	list_for_each_entry(obj_priv, &dev_priv->mm.active_list, list) {

		if (obj_priv->pin_count > 0)

			args->aper_available_size -= obj_priv->obj->size;

	}



	return 0;

}





/**

 * Creates a new mm object and returns a handle to it.

drivers/gpu/drm/radeon/radeon_cp.c

+8 −7
Original line number Diff line number Diff line
@@ -653,15 +653,16 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, 
	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);



	/* Turn on bus mastering */

	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||

	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||

	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {

		/* rs400, rs690/rs740 */

		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;

		/* rs600/rs690/rs740 */

		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;

		RADEON_WRITE(RADEON_BUS_CNTL, tmp);

	} else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||

		    ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {

		/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */

	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||

		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {

		/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */

		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;

		RADEON_WRITE(RADEON_BUS_CNTL, tmp);

	} /* PCIE cards appears to not need this */