Merge "clk: qcom: gdsc-regulator: Add support to toggle the SW_COLLAPSE bit" into msm-4.9 (30743efb) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -59,6 +59,8 @@ Optional properties:
		- qcom,poll-cfg-gdscr: Poll the CFG register of the GDSC to determine if the
		GDSC is enabled/disabled. This flag should not be set
		in conjunction with "hw-ctrl-addr".
		- qcom,toggle-sw-collapse-in-disable: If set, SW_COLLAPSE bit is toggled
		in disable call.

		Example:
		gdsc_oxili_gx: qcom,gdsc@fd8c4024 {

drivers/clk/qcom/gdsc-regulator.c

+18 −2

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
		* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -54,6 +54,9 @@
		/* Timeout Delay */
		#define TIMEOUT_US 100

		/* TOGGLE SW COLLAPSE */
		#define TOGGLE_SW_COLLAPSE_IN_DISABLE BIT(0)

		struct gdsc {
		struct regulator_dev *rdev;
		struct regulator_desc rdesc;
		@@ -79,6 +82,7 @@ struct gdsc {
		int reset_count;
		int root_clk_idx;
		u32 gds_timeout;
		u32 flags;
		};

		enum gdscr_status {
		@@ -378,6 +382,13 @@ static int gdsc_disable(struct regulator_dev *rdev)
		regval \|= SW_COLLAPSE_MASK;
		regmap_write(sc->regmap, REG_OFFSET, regval);

		if (sc->flags & TOGGLE_SW_COLLAPSE_IN_DISABLE) {
		regval &= ~SW_COLLAPSE_MASK;
		regmap_write(sc->regmap, REG_OFFSET, regval);
		regval \|= SW_COLLAPSE_MASK;
		regmap_write(sc->regmap, REG_OFFSET, regval);
		}

		/* Wait for 8 XO cycles before polling the status bit. */
		mb();
		udelay(1);
		@@ -522,7 +533,7 @@ static int gdsc_probe(struct platform_device *pdev)
		struct resource *res;
		struct gdsc *sc;
		uint32_t regval, clk_dis_wait_val = 0;
		bool retain_mem, retain_periph, support_hw_trigger;
		bool retain_mem, retain_periph, support_hw_trigger, prop_val;
		int i, ret;
		u32 timeout;

		@@ -613,6 +624,11 @@ static int gdsc_probe(struct platform_device *pdev)
		sc->force_root_en = of_property_read_bool(pdev->dev.of_node,
		"qcom,force-enable-root-clk");

		prop_val = of_property_read_bool(pdev->dev.of_node,
		"qcom,toggle-sw-collapse-in-disable");
		if (prop_val)
		sc->flags \|= TOGGLE_SW_COLLAPSE_IN_DISABLE;

		for (i = 0; i < sc->clock_count; i++) {
		const char *clock_name;