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Commit 301c9f26 authored by Devin Heitmueller's avatar Devin Heitmueller Committed by Mauro Carvalho Chehab
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[media] au8522: Handle differences in comb filter config for s-video input 



Tweak the comb filter config when in s-video mode to match the Hauppauge
Windows driver values (based on register dumps).

This work was sponsored by GetWellNetwork Inc.

Signed-off-by: default avatarDevin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent d2c194ce

drivers/media/dvb/frontends/au8522_decoder.c

+12 −4
Original line number Diff line number Diff line
@@ -278,10 +278,18 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode) 
			AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);

	au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,

			AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);

	if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||

	    input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {

		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,

				AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);

		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,

				AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);

	} else {

		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,

				AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);

		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,

				AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);

	}

	au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,

			AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);

	au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,

drivers/media/dvb/frontends/au8522_priv.h

+2 −0
Original line number Diff line number Diff line
@@ -397,7 +397,9 @@ void au8522_release_state(struct au8522_state *state); 
#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS		0x0A

#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS		0x32

#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS		0x34

#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO		0x2a

#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS		0x05

#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO		0x15

#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS		0x6E

#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS			0x0F

#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS		0x80