Merge "ARM: dts: mdm: Add initial device node support for MDM9607" (2fa38bef) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/arm/msm/msm.txt

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		@@ -366,3 +366,4 @@ compatible = "qcom,apq8009-mtp"
		compatible = "qcom,sdxpoorwills-rumi"
		compatible = "qcom,sdxpoorwills-mtp"
		compatible = "qcom,sdxpoorwills-cdp"
		compatible = "qcom,mdm9607-ttp"

Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.txt

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		Qualcomm Technologies, Inc. MDM9607 TLMM block

		This binding describes the Top Level Mode Multiplexer block found in the
		MDM9607 platform.

		- compatible:
		Usage: required
		Value type: <string>
		Definition: must be "qcom,mdm9607-pinctrl"

		- reg:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: the base address and size of the TLMM register space.

		- interrupts:
		Usage: required
		Value type: <prop-encoded-array>
		Definition: should specify the TLMM summary IRQ.

		- interrupt-controller:
		Usage: required
		Value type: <none>
		Definition: identifies this node as an interrupt controller

		- #interrupt-cells:
		Usage: required
		Value type: <u32>
		Definition: must be 2. Specifying the pin number and flags, as defined
		in <dt-bindings/interrupt-controller/irq.h>

		- gpio-controller:
		Usage: required
		Value type: <none>
		Definition: identifies this node as a gpio controller

		- #gpio-cells:
		Usage: required
		Value type: <u32>
		Definition: must be 2. Specifying the pin number and flags, as defined
		in <dt-bindings/gpio/gpio.h>

		- qcom,tlmm-emmc-boot-select:
		Usage: optional
		Value type: <u32>
		Definition: selects the bit-field position to set.

		Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
		a general description of GPIO and interrupt bindings.

		Please refer to pinctrl-bindings.txt in this directory for details of the
		common pinctrl bindings used by client devices, including the meaning of the
		phrase "pin configuration node".

		The pin configuration nodes act as a container for an arbitrary number of
		subnodes. Each of these subnodes represents some desired configuration for a
		pin, a group, or a list of pins or groups. This configuration can include the
		mux function to select on those pin(s)/group(s), and various pin configuration
		parameters, such as pull-up, drive strength, etc.


		PIN CONFIGURATION NODES:

		The name of each subnode is not important; all subnodes should be enumerated
		and processed purely based on their content.

		Each subnode only affects those parameters that are explicitly listed. In
		other words, a subnode that lists a mux function but no pin configuration
		parameters implies no information about any pin configuration parameters.
		Similarly, a pin subnode that describes a pullup parameter implies no
		information about e.g. the mux function.


		The following generic properties as defined in pinctrl-bindings.txt are valid
		to specify in a pin configuration subnode:

		- pins:
		Usage: required
		Value type: <string-array>
		Definition: List of gpio pins affected by the properties specified in
		this subnode. Valid pins are:
		gpio0-gpio79,
		sdc1_clk,
		sdc1_cmd,
		sdc1_data,
		sdc2_clk,
		sdc2_cmd,
		sdc2_data,
		qdsd_clk,
		qdsd_cmd,
		qdsd_data0,
		qdsd_data1,
		qdsd_data2,
		qdsd_data3

		- function:
		Usage: required
		Value type: <string>
		Definition: Specify the alternative function to be configured for the
		specified pins. Functions are only valid for gpio pins.
		Valid values are:

		blsp_spi3, blsp_uart3, qdss_tracedata_a, bimc_dte1, blsp_i2c3,
		qdss_traceclk_a, bimc_dte0, qdss_cti_trig_in_a1, blsp_spi2,
		blsp_uart2, blsp_uim2, blsp_i2c2, qdss_tracectl_a, sensor_int2,
		blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, sensor_int3, sensor_en,
		blsp_i2c5, ebi2_a, qdss_tracedata_b, sensor_rst, blsp2_spi,
		blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b,
		gcc_gp3_clk_b, blsp_i2c1, gcc_gp1_clk_b, blsp_spi4, blsp_uart4,
		rcm_marker1, blsp_i2c4, qdss_cti_trig_out_a1, rcm_marker2,
		qdss_cti_trig_out_a0, blsp_spi6, blsp_uart6, pri_mi2s_ws_a,
		ebi2_lcd_te_b, blsp1_spi, backlight_en_b, pri_mi2s_data0_a,
		pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, pri_mi2s_sck_a,
		ebi2_lcd_cs_n_b, touch_rst, pri_mi2s_mclk_a, pwr_nav_enabled_a,
		ts_int, sd_write, pwr_crypto_enabled_a, codec_rst, adsp_ext,
		atest_combodac_to_gpio_native, uim2_data, gmac_mdio, gcc_gp1_clk_a,
		uim2_clk, gcc_gp2_clk_a, eth_irq, uim2_reset, gcc_gp3_clk_a,
		eth_rst, uim2_present, prng_rosc, uim1_data, uim1_clk,
		uim1_reset, uim1_present, gcc_plltest, uim_batt, coex_uart,
		codec_int, qdss_cti_trig_in_a0, atest_bbrx1, cri_trng0, atest_bbrx0,
		cri_trng, qdss_cti_trig_in_b0, atest_gpsadc_dtest0_native,
		qdss_cti_trig_out_b0, qdss_tracectl_b, qdss_traceclk_b, pa_indicator,
		modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a,
		gsm0_tx, qdss_cti_trig_in_b1, cri_trng1, qdss_cti_trig_out_b1,
		ssbi1, atest_gpsadc_dtest1_native, ssbi2, atest_char3, atest_char2,
		atest_char1, atest_char0, atest_char, ebi0_wrcdc, ldo_update,
		gcc_tlmm, ldo_en, dbg_out, atest_tsens, lcd_rst, wlan_en1,
		nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, pbs0, sec_mi2s,
		pwr_modem_enabled_a, pbs1, pwr_modem_enabled_b, pbs2, pwr_nav_enabled_b,
		pwr_crypto_enabled_b, gpio

		- bias-disable:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configued as no pull.

		- bias-pull-down:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configued as pull down.

		- bias-pull-up:
		Usage: optional
		Value type: <none>
		Definition: The specified pins should be configued as pull up.

		- output-high:
		Usage: optional
		Value type: <none>
		Definition: The specified pins are configured in output mode, driven
		high.
		Not valid for sdc pins.

		- output-low:
		Usage: optional
		Value type: <none>
		Definition: The specified pins are configured in output mode, driven
		low.
		Not valid for sdc pins.

		- drive-strength:
		Usage: optional
		Value type: <u32>
		Definition: Selects the drive strength for the specified pins, in mA.
		Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16

		Example:

		tlmm: pinctrl@01010000 {
		compatible = "qcom,mdm9607-pinctrl";
		reg = <0x01010000 0x300000>;
		interrupts = <0 208 0>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		qcom,tlmm-emmc-boot-select = <0x1>;

		uart_console_active: uart_console_active {
		mux {
		pins = "gpio8", "gpio9";
		function = "blsp_uart5";
		};

		config {
		pins = "gpio8", "gpio9";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

arch/arm/boot/dts/qcom/Makefile

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		@@ -12,6 +12,9 @@ dtb-$(CONFIG_ARCH_MDM9650) += mdm9650-nand-mtp.dtb \
		mdm9650-v1.1-nand-mtp.dtb \
		mdm9650-v1.1-nand-cv2x.dtb

		dtb-$(CONFIG_ARCH_MDM9607) += mdm9607-mtp.dtb \
		mdm9607-ttp.dtb

		targets += dtbs
		targets += $(addprefix ../, $(dtb-y))

arch/arm/boot/dts/qcom/mdm9607-bus.dtsi

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		/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		* only version 2 as published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*/

		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/* Version = 1 */
		ad_hoc_bus: ad-hoc-bus {
		compatible = "qcom,msm-bus-device";
		reg = <0x401000 0x58000>,
		<0x500000 0x15080>;
		reg-names = "bimc-base", "pcnoc-base";

		/* Buses */

		fab_bimc: fab-bimc {
		cell-id = <MSM_BUS_FAB_BIMC>;
		label = "fab-bimc";
		qcom,fab-dev;
		qcom,base-name = "bimc-base";
		qcom,bus-type = <2>;
		qcom,util-fact = <154>;
		clock-names = "bus_clk", "bus_a_clk";
		clocks = <&clock_gcc clk_bimc_msmbus_clk>,
		<&clock_gcc clk_bimc_msmbus_a_clk>;

		coresight-id = <203>;
		coresight-name = "coresight-bimc";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in0>;
		coresight-child-ports = <3>;
		};

		fab_pcnoc: fab-pcnoc {
		cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
		label = "fab-pcnoc";
		qcom,fab-dev;
		qcom,base-name = "pcnoc-base";
		qcom,base-offset = <0x7000>;
		qcom,qos-off = <0x1000>;
		qcom,bus-type = <1>;
		clock-names = "bus_clk", "bus_a_clk";
		clocks = <&clock_gcc clk_pcnoc_msmbus_clk>,
		<&clock_gcc clk_pcnoc_msmbus_a_clk>;

		coresight-id = <201>;
		coresight-name = "coresight-pcnoc";
		coresight-nr-inports = <0>;
		coresight-outports = <0>;
		coresight-child-list = <&funnel_in2>;
		coresight-child-ports = <0>;
		};

		/* Masters */

		mas_apps_proc: mas-apps-proc {
		cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
		label = "mas-apps-proc";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,qport = <0>;
		qcom,qos-mode = "fixed";
		qcom,connections = < &slv_bimc_pcnoc &slv_ebi>;
		qcom,prio-lvl = <0>;
		qcom,prio-rd = <0>;
		qcom,prio-wr = <0>;
		qcom,bus-dev = <&fab_bimc>;
		qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
		};

		mas_pcnoc_bimc_1: mas-pcnoc-bimc-1 {
		cell-id = <MSM_BUS_MASTER_PCNOC_BIMC_1>;
		label = "mas-pcnoc-bimc-1";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_ebi>;
		qcom,bus-dev = <&fab_bimc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_BIMC_1>;
		};

		mas_tcu_0: mas-tcu-0 {
		cell-id = <MSM_BUS_MASTER_TCU_0>;
		label = "mas-tcu-0";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,qport = <5>;
		qcom,qos-mode = "fixed";
		qcom,connections = <&slv_ebi>;
		qcom,prio-lvl = <2>;
		qcom,prio-rd = <2>;
		qcom,prio-wr = <2>;
		qcom,bus-dev = <&fab_bimc>;
		qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
		};

		mas_qdss_bam: mas-qdss-bam {
		cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
		label = "mas-qdss-bam";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&qdss_int>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
		qcom,blacklist = <&pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
		&pcnoc_s_4 &pcnoc_s_5 &pcnoc_s_3 &slv_tcu>;
		};

		mas_bimc_pcnoc: mas-bimc-pcnoc {
		cell-id = <MSM_BUS_MASTER_BIMC_PCNOC>;
		label = "mas-bimc-pcnoc";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_int_0
		&pcnoc_int_2 &slv_cats_0>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_BIMC_PCNOC>;
		};

		mas_qdss_etr: mas-qdss-etr {
		cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
		label = "mas-qdss-etr";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&qdss_int>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
		&pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5
		&slv_crypto_0_cfg &slv_message_ram
		&slv_pdm &slv_prng &slv_qdss_stm
		&slv_tcu>;
		};

		mas_audio: mas-audio {
		cell-id = <MSM_BUS_MASTER_AUDIO>;
		label = "mas-audio";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_m_0>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_AUDIO>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1
		&pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu>;
		};

		mas_qpic: mas-qpic {
		cell-id = <MSM_BUS_MASTER_QPIC>;
		label = "mas-qpic";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_m_0>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_QPIC>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
		&pcnoc_s_3 &pcnoc_s_4
		&pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg &slv_pdm
		&slv_prng &slv_usb2 >;
		};

		mas_hsic: mas-hsic {
		cell-id = <MSM_BUS_MASTER_USB_HSIC>;
		label = "mas-hsic";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_m_0>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_USB_HSIC>;
		};

		mas_blsp_1: mas-blsp-1 {
		cell-id = <MSM_BUS_MASTER_BLSP_1>;
		label = "mas-blsp-1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_m_1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1
		&pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu >;
		};

		mas_usb_hs1: mas-usb-hs1 {
		cell-id = <MSM_BUS_MASTER_USB_HS>;
		label = "mas-usb-hs1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_m_1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4
		&pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg
		&slv_pdm &slv_prng &slv_usb2
		&slv_usb_phy> ;
		};

		mas_crypto: mas-crypto {
		cell-id = <MSM_BUS_MASTER_CRYPTO>;
		label = "mas-crypto";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,qport = <0>;
		qcom,qos-mode = "fixed";
		qcom,connections = <&pcnoc_int_3>;
		qcom,prio1 = <2>;
		qcom,prio0 = <2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg &slv_pdm
		&slv_usb2 &slv_prng>;
		};

		mas_sdcc_1: mas-sdcc-1 {
		cell-id = <MSM_BUS_MASTER_SDCC_1>;
		label = "mas-sdcc-1";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_int_3>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg &slv_pdm
		&slv_usb2 &slv_prng>;
		};

		mas_sdcc_2: mas-sdcc-2 {
		cell-id = <MSM_BUS_MASTER_SDCC_2>;
		label = "mas-sdcc-2";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_int_3>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg &slv_pdm
		&slv_usb2 &slv_prng>;
		};

		mas_xi_usb_hs1: mas-xi-usb-hs1 {
		cell-id = <MSM_BUS_MASTER_XM_USB_HS1>;
		label = "mas-xi-usb-hs1";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4
		&pcnoc_s_5 &slv_tcu &slv_crypto_0_cfg
		&slv_pdm &slv_usb2 &slv_prng
		&slv_usb_phy>;
		};

		mas_xi_hsic: mas-xi-hsic {
		cell-id = <MSM_BUS_MASTER_XI_USB_HSIC>;
		label = "mas-xi-hsic";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_XI_HSIC>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
		&pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5
		&slv_tcu &slv_crypto_0_cfg
		&slv_pdm &slv_usb2 &slv_prng>;
		};

		mas_sgmii: mas-sgmii {
		cell-id = <MSM_BUS_MASTER_SGMII>;
		label = "mas-sgmii";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,qport = <10>;
		qcom,qos-mode = "fixed";
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,prio1 = <1>;
		qcom,prio0 = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_SGMII>;
		qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
		&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
		&slv_crypto_0_cfg &slv_pdm
		&slv_usb2 &slv_prng>;
		};

		/* Internal nodes */

		pcnoc_m_0: pcnoc-m-0 {
		cell-id = <MSM_BUS_PNOC_M_0>;
		label = "pcnoc-m-0";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
		};

		pcnoc_m_1: pcnoc-m-1 {
		cell-id = <MSM_BUS_PNOC_M_1>;
		label = "pcnoc-m-1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
		};

		qdss_int: qdss-int {
		cell-id = <MSM_BUS_SNOC_QDSS_INT>;
		label = "qdss-int";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_int_0 &slv_pcnoc_bimc_1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
		qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
		};

		pcnoc_int_0: pcnoc-int-0 {
		cell-id = <MSM_BUS_PNOC_INT_0>;
		label = "pcnoc-int-0";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,connections = <&slv_imem &slv_qdss_stm>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
		};

		pcnoc_int_2: pcnoc-int-2 {
		cell-id = <MSM_BUS_PNOC_INT_2>;
		label = "pcnoc-int-2";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&pcnoc_s_1 &pcnoc_s_2
		&pcnoc_s_0 &pcnoc_s_4
		&pcnoc_s_5 &pcnoc_s_3
		&slv_tcu >;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>;
		};

		pcnoc_int_3: pcnoc-int-3 {
		cell-id = <MSM_BUS_PNOC_INT_3>;
		label = "pcnoc-int-3";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>;
		};

		pcnoc_s_0: pcnoc-s-0 {
		cell-id = <MSM_BUS_PNOC_SLV_0>;
		label = "pcnoc-s-0";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_tcsr &slv_sdcc_1 &slv_blsp_1
		&slv_sgmii>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
		};

		pcnoc_s_1: pcnoc-s-1 {
		cell-id = <MSM_BUS_PNOC_SLV_1>;
		label = "pcnoc-s-1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_usb2 &slv_crypto_0_cfg
		&slv_prng &slv_pdm
		&slv_message_ram>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
		};

		pcnoc_s_2: pcnoc-s-2 {
		cell-id = <MSM_BUS_PNOC_SLV_2>;
		label = "pcnoc-s-2";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_hsic &slv_sdcc_2 &slv_audio>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
		};

		pcnoc_s_3: pcnoc-s-3 {
		cell-id = <MSM_BUS_PNOC_SLV_3>;
		label = "pcnoc-s-3";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,connections = <&slv_usb_phy>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
		};

		pcnoc_s_4: pcnoc-s-4 {
		cell-id = <MSM_BUS_PNOC_SLV_4>;
		label = "pcnoc-s-4";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_imem_cfg &slv_pmic_arb>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
		};

		pcnoc_s_5: pcnoc-s-5 {
		cell-id = <MSM_BUS_PNOC_SLV_5>;
		label = "pcnoc-s-5";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,connections = <&slv_tlmm>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
		};

		/* Slaves */

		slv_ebi:slv-ebi {
		cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
		label = "slv-ebi";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_bimc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
		};

		slv_bimc_pcnoc:slv-bimc-pcnoc {
		cell-id = <MSM_BUS_SLAVE_BIMC_PCNOC>;
		label = "slv-bimc-pcnoc";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_bimc>;
		qcom,connections = <&mas_bimc_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_PCNOC>;
		};

		slv_pcnoc_bimc_1:slv-pcnoc-bimc-1 {
		cell-id = <MSM_BUS_SLAVE_PCNOC_BIMC_1>;
		label = "slv-pcnoc-bimc-1";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,connections = <&mas_pcnoc_bimc_1>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_BIMC_1>;
		};

		slv_qdss_stm:slv-qdss-stm {
		cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
		label = "slv-qdss-stm";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
		};

		slv_cats_0:slv-cats-0 {
		cell-id = <MSM_BUS_SLAVE_CATS_128>;
		label = "slv-cats-0";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>;
		};

		slv_imem:slv-imem {
		cell-id = <MSM_BUS_SLAVE_SYSTEM_IMEM>;
		label = "slv-imem";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
		};

		slv_tcsr:slv-tcsr {
		cell-id = <MSM_BUS_SLAVE_TCSR>;
		label = "slv-tcsr";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
		};

		slv_sdcc_1:slv-sdcc-1 {
		cell-id = <MSM_BUS_SLAVE_SDCC_1>;
		label = "slv-sdcc-1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
		};

		slv_blsp_1:slv-blsp-1 {
		cell-id = <MSM_BUS_SLAVE_BLSP_1>;
		label = "slv-blsp-1";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
		};

		slv_sgmii:slv-sgmii {
		cell-id = <MSM_BUS_SLAVE_SGMII>;
		label = "slv-sgmii";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_SGMII>;
		};

		slv_crypto_0_cfg:slv-crypto-0-cfg {
		cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
		label = "slv-crypto-0-cfg";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
		};

		slv_message_ram:slv-message-ram {
		cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
		label = "slv-message-ram";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
		};

		slv_pdm:slv-pdm {
		cell-id = <MSM_BUS_SLAVE_PDM>;
		label = "slv-pdm";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
		};

		slv_prng:slv-prng {
		cell-id = <MSM_BUS_SLAVE_PRNG>;
		label = "slv-prng";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
		};

		slv_usb2:slv-usb2 {
		cell-id = <MSM_BUS_SLAVE_USB_HS>;
		label = "slv-usb2";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
		};

		slv_sdcc_2:slv-sdcc-2 {
		cell-id = <MSM_BUS_SLAVE_SDCC_2>;
		label = "slv-sdcc-2";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
		};

		slv_audio:slv-audio {
		cell-id = <MSM_BUS_SLAVE_AUDIO>;
		label = "slv-audio";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_AUDIO>;
		};

		slv_hsic:slv-hsic {
		cell-id = <MSM_BUS_SLAVE_USB_HSIC>;
		label = "slv-hsic";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_USB_HSIC>;
		};

		slv_usb_phy:slv-usb-phy {
		cell-id = <MSM_BUS_SLAVE_USB_PHYS_CFG>;
		label = "slv-usb-phy";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_USB_PHY_CFG>;
		};

		slv_tlmm:slv-tlmm {
		cell-id = <MSM_BUS_SLAVE_TLMM>;
		label = "slv-tlmm";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
		};

		slv_imem_cfg:slv-imem-cfg {
		cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
		label = "slv-imem-cfg";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
		};

		slv_pmic_arb:slv-pmic-arb {
		cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
		label = "slv-pmic-arb";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
		};

		slv_tcu:slv-tcu {
		cell-id = <MSM_BUS_SLAVE_TCU>;
		label = "slv-tcu";
		qcom,buswidth = <8>;
		qcom,agg-ports = <1>;
		qcom,ap-owned;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
		};

		slv_qipc {
		cell-id = <MSM_BUS_SLAVE_QPIC>;
		label = "slv-qpic";
		qcom,buswidth = <4>;
		qcom,agg-ports = <1>;
		qcom,bus-dev = <&fab_pcnoc>;
		qcom,slv-rpm-id = <ICBID_SLAVE_QPIC>;
		};
		};
		};

arch/arm/boot/dts/qcom/mdm9607-cdp.dts

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