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Commit 2f73bfbe authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
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MIPS: Alchemy: remove au_read/write/sync 



replace au_read/write/sync with __raw_read/write and wmb.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7465/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 9cf12167

arch/mips/alchemy/common/dbdma.c

+11 −11
Original line number Diff line number Diff line
@@ -341,7 +341,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 
			(dtp->dev_flags & DEV_FLAGS_SYNC))

				i |= DDMA_CFG_SYNC;

		cp->ddma_cfg = i;

		au_sync();

		wmb(); /* drain writebuffer */



		/*

		 * Return a non-zero value that can be used to find the channel
@@ -631,7 +631,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 
	 */

	dma_cache_wback_inv((unsigned long)buf, nbytes);

	dp->dscr_cmd0 |= DSCR_CMD0_V;	/* Let it rip */

	au_sync();

	wmb(); /* drain writebuffer */

	dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));

	ctp->chan_ptr->ddma_dbell = 0;
@@ -693,7 +693,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) 
	 */

	dma_cache_inv((unsigned long)buf, nbytes);

	dp->dscr_cmd0 |= DSCR_CMD0_V;	/* Let it rip */

	au_sync();

	wmb(); /* drain writebuffer */

	dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));

	ctp->chan_ptr->ddma_dbell = 0;
@@ -760,7 +760,7 @@ void au1xxx_dbdma_stop(u32 chanid) 


	cp = ctp->chan_ptr;

	cp->ddma_cfg &= ~DDMA_CFG_EN;	/* Disable channel */

	au_sync();

	wmb(); /* drain writebuffer */

	while (!(cp->ddma_stat & DDMA_STAT_H)) {

		udelay(1);

		halt_timeout++;
@@ -771,7 +771,7 @@ void au1xxx_dbdma_stop(u32 chanid) 
	}

	/* clear current desc valid and doorbell */

	cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);

	au_sync();

	wmb(); /* drain writebuffer */

}

EXPORT_SYMBOL(au1xxx_dbdma_stop);
@@ -789,9 +789,9 @@ void au1xxx_dbdma_start(u32 chanid) 
	cp = ctp->chan_ptr;

	cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);

	cp->ddma_cfg |= DDMA_CFG_EN;	/* Enable channel */

	au_sync();

	wmb(); /* drain writebuffer */

	cp->ddma_dbell = 0;

	au_sync();

	wmb(); /* drain writebuffer */

}

EXPORT_SYMBOL(au1xxx_dbdma_start);
@@ -832,7 +832,7 @@ u32 au1xxx_get_dma_residue(u32 chanid) 


	/* This is only valid if the channel is stopped. */

	rv = cp->ddma_bytecnt;

	au_sync();

	wmb(); /* drain writebuffer */



	return rv;

}
@@ -868,7 +868,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) 
	au1x_dma_chan_t *cp;



	intstat = dbdma_gptr->ddma_intstat;

	au_sync();

	wmb(); /* drain writebuffer */

	chan_index = __ffs(intstat);



	ctp = chan_tab_ptr[chan_index];
@@ -877,7 +877,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) 


	/* Reset interrupt. */

	cp->ddma_irq = 0;

	au_sync();

	wmb(); /* drain writebuffer */



	if (ctp->chan_callback)

		ctp->chan_callback(irq, ctp->chan_callparam);
@@ -1061,7 +1061,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable) 
	dbdma_gptr->ddma_config = 0;

	dbdma_gptr->ddma_throttle = 0;

	dbdma_gptr->ddma_inten = 0xffff;

	au_sync();

	wmb(); /* drain writebuffer */



	ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);

	if (ret)

arch/mips/alchemy/common/dma.c

+8 −7
Original line number Diff line number Diff line
@@ -141,17 +141,17 @@ void dump_au1000_dma_channel(unsigned int dmanr) 


	printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);

	printk(KERN_INFO "  mode = 0x%08x\n",

	       au_readl(chan->io + DMA_MODE_SET));

	       __raw_readl(chan->io + DMA_MODE_SET));

	printk(KERN_INFO "  addr = 0x%08x\n",

	       au_readl(chan->io + DMA_PERIPHERAL_ADDR));

	       __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));

	printk(KERN_INFO "  start0 = 0x%08x\n",

	       au_readl(chan->io + DMA_BUFFER0_START));

	       __raw_readl(chan->io + DMA_BUFFER0_START));

	printk(KERN_INFO "  start1 = 0x%08x\n",

	       au_readl(chan->io + DMA_BUFFER1_START));

	       __raw_readl(chan->io + DMA_BUFFER1_START));

	printk(KERN_INFO "  count0 = 0x%08x\n",

	       au_readl(chan->io + DMA_BUFFER0_COUNT));

	       __raw_readl(chan->io + DMA_BUFFER0_COUNT));

	printk(KERN_INFO "  count1 = 0x%08x\n",

	       au_readl(chan->io + DMA_BUFFER1_COUNT));

	       __raw_readl(chan->io + DMA_BUFFER1_COUNT));

}



/*
@@ -204,7 +204,8 @@ int request_au1000_dma(int dev_id, const char *dev_str, 
	}



	/* fill it in */

	chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;

	chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +

			i * DMA_CHANNEL_LEN);

	chan->dev_id = dev_id;

	chan->dev_str = dev_str;

	chan->fifo_addr = dev->fifo_addr;

arch/mips/include/asm/mach-au1x00/au1000.h

+0 −48
Original line number Diff line number Diff line
@@ -645,54 +645,6 @@ 


#include <asm/cpu.h>



/* cpu pipeline flush */

void static inline au_sync(void)

{

	__asm__ volatile ("sync");

}



void static inline au_sync_udelay(int us)

{

	__asm__ volatile ("sync");

	udelay(us);

}



void static inline au_sync_delay(int ms)

{

	__asm__ volatile ("sync");

	mdelay(ms);

}



void static inline au_writeb(u8 val, unsigned long reg)

{

	*(volatile u8 *)reg = val;

}



void static inline au_writew(u16 val, unsigned long reg)

{

	*(volatile u16 *)reg = val;

}



void static inline au_writel(u32 val, unsigned long reg)

{

	*(volatile u32 *)reg = val;

}



static inline u8 au_readb(unsigned long reg)

{

	return *(volatile u8 *)reg;

}



static inline u16 au_readw(unsigned long reg)

{

	return *(volatile u16 *)reg;

}



static inline u32 au_readl(unsigned long reg)

{

	return *(volatile u32 *)reg;

}



/* helpers to access the SYS_* registers */

static inline unsigned long alchemy_rdsys(int regofs)

{

arch/mips/include/asm/mach-au1x00/au1000_dma.h

+25 −25
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ enum { 
struct dma_chan {

	int dev_id;		/* this channel is allocated if >= 0, */

				/* free otherwise */

	unsigned int io;

	void __iomem *io;

	const char *dev_str;

	int irq;

	void *irq_dev;
@@ -157,7 +157,7 @@ static inline void enable_dma_buffer0(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_BE0, chan->io + DMA_MODE_SET);

	__raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);

}



static inline void enable_dma_buffer1(unsigned int dmanr)
@@ -166,7 +166,7 @@ static inline void enable_dma_buffer1(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_BE1, chan->io + DMA_MODE_SET);

	__raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);

}

static inline void enable_dma_buffers(unsigned int dmanr)

{
@@ -174,7 +174,7 @@ static inline void enable_dma_buffers(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);

	__raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);

}



static inline void start_dma(unsigned int dmanr)
@@ -183,7 +183,7 @@ static inline void start_dma(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_GO, chan->io + DMA_MODE_SET);

	__raw_writel(DMA_GO, chan->io + DMA_MODE_SET);

}



#define DMA_HALT_POLL 0x5000
@@ -195,11 +195,11 @@ static inline void halt_dma(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);

	__raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);



	/* Poll the halt bit */

	for (i = 0; i < DMA_HALT_POLL; i++)

		if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)

		if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)

			break;

	if (i == DMA_HALT_POLL)

		printk(KERN_INFO "halt_dma: HALT poll expired!\n");
@@ -215,7 +215,7 @@ static inline void disable_dma(unsigned int dmanr) 
	halt_dma(dmanr);



	/* Now we can disable the buffers */

	au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);

	__raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);

}



static inline int dma_halted(unsigned int dmanr)
@@ -224,7 +224,7 @@ static inline int dma_halted(unsigned int dmanr) 


	if (!chan)

		return 1;

	return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;

	return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;

}



/* Initialize a DMA channel. */
@@ -239,14 +239,14 @@ static inline void init_dma(unsigned int dmanr) 
	disable_dma(dmanr);



	/* Set device FIFO address */

	au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);

	__raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);



	mode = chan->mode | (chan->dev_id << DMA_DID_BIT);

	if (chan->irq)

		mode |= DMA_IE;



	au_writel(~mode, chan->io + DMA_MODE_CLEAR);

	au_writel(mode,	 chan->io + DMA_MODE_SET);

	__raw_writel(~mode, chan->io + DMA_MODE_CLEAR);

	__raw_writel(mode,	 chan->io + DMA_MODE_SET);

}



/*
@@ -283,7 +283,7 @@ static inline int get_dma_active_buffer(unsigned int dmanr) 


	if (!chan)

		return -1;

	return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;

	return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;

}



/*
@@ -304,7 +304,7 @@ static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a) 
	if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)

		return;



	au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);

	__raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);

}



/*
@@ -316,7 +316,7 @@ static inline void clear_dma_done0(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);

	__raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);

}



static inline void clear_dma_done1(unsigned int dmanr)
@@ -325,7 +325,7 @@ static inline void clear_dma_done1(unsigned int dmanr) 


	if (!chan)

		return;

	au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);

	__raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);

}



/*
@@ -344,7 +344,7 @@ static inline void set_dma_addr0(unsigned int dmanr, unsigned int a) 


	if (!chan)

		return;

	au_writel(a, chan->io + DMA_BUFFER0_START);

	__raw_writel(a, chan->io + DMA_BUFFER0_START);

}



/*
@@ -356,7 +356,7 @@ static inline void set_dma_addr1(unsigned int dmanr, unsigned int a) 


	if (!chan)

		return;

	au_writel(a, chan->io + DMA_BUFFER1_START);

	__raw_writel(a, chan->io + DMA_BUFFER1_START);

}
@@ -370,7 +370,7 @@ static inline void set_dma_count0(unsigned int dmanr, unsigned int count) 
	if (!chan)

		return;

	count &= DMA_COUNT_MASK;

	au_writel(count, chan->io + DMA_BUFFER0_COUNT);

	__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);

}



/*
@@ -383,7 +383,7 @@ static inline void set_dma_count1(unsigned int dmanr, unsigned int count) 
	if (!chan)

		return;

	count &= DMA_COUNT_MASK;

	au_writel(count, chan->io + DMA_BUFFER1_COUNT);

	__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);

}



/*
@@ -396,8 +396,8 @@ static inline void set_dma_count(unsigned int dmanr, unsigned int count) 
	if (!chan)

		return;

	count &= DMA_COUNT_MASK;

	au_writel(count, chan->io + DMA_BUFFER0_COUNT);

	au_writel(count, chan->io + DMA_BUFFER1_COUNT);

	__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);

	__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);

}



/*
@@ -410,7 +410,7 @@ static inline unsigned int get_dma_buffer_done(unsigned int dmanr) 


	if (!chan)

		return 0;

	return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);

	return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);

}
@@ -437,10 +437,10 @@ static inline int get_dma_residue(unsigned int dmanr) 
	if (!chan)

		return 0;



	curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?

	curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?

	    DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;



	count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;

	count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;



	if ((chan->mode & DMA_DW_MASK) == DMA_DW16)

		count <<= 1;

drivers/mmc/host/au1xmmc.c

+86 −81
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ struct au1xmmc_host { 
	struct mmc_request *mrq;



	u32 flags;

	u32 iobase;

	void __iomem *iobase;

	u32 clock;

	u32 bus_width;

	u32 power_mode;
@@ -162,32 +162,33 @@ static inline int has_dbdma(void) 


static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)

{

	u32 val = au_readl(HOST_CONFIG(host));

	u32 val = __raw_readl(HOST_CONFIG(host));

	val |= mask;

	au_writel(val, HOST_CONFIG(host));

	au_sync();

	__raw_writel(val, HOST_CONFIG(host));

	wmb(); /* drain writebuffer */

}



static inline void FLUSH_FIFO(struct au1xmmc_host *host)

{

	u32 val = au_readl(HOST_CONFIG2(host));

	u32 val = __raw_readl(HOST_CONFIG2(host));



	au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));

	au_sync_delay(1);

	__raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */

	mdelay(1);



	/* SEND_STOP will turn off clock control - this re-enables it */

	val &= ~SD_CONFIG2_DF;



	au_writel(val, HOST_CONFIG2(host));

	au_sync();

	__raw_writel(val, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */

}



static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)

{

	u32 val = au_readl(HOST_CONFIG(host));

	u32 val = __raw_readl(HOST_CONFIG(host));

	val &= ~mask;

	au_writel(val, HOST_CONFIG(host));

	au_sync();

	__raw_writel(val, HOST_CONFIG(host));

	wmb(); /* drain writebuffer */

}



static inline void SEND_STOP(struct au1xmmc_host *host)
@@ -197,12 +198,13 @@ static inline void SEND_STOP(struct au1xmmc_host *host) 
	WARN_ON(host->status != HOST_S_DATA);

	host->status = HOST_S_STOP;



	config2 = au_readl(HOST_CONFIG2(host));

	au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));

	au_sync();

	config2 = __raw_readl(HOST_CONFIG2(host));

	__raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */



	/* Send the stop command */

	au_writel(STOP_CMD, HOST_CMD(host));

	__raw_writel(STOP_CMD, HOST_CMD(host));

	wmb(); /* drain writebuffer */

}



static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
@@ -296,28 +298,28 @@ static int au1xmmc_send_command(struct au1xmmc_host *host, int wait, 
		}

	}



	au_writel(cmd->arg, HOST_CMDARG(host));

	au_sync();

	__raw_writel(cmd->arg, HOST_CMDARG(host));

	wmb(); /* drain writebuffer */



	if (wait)

		IRQ_OFF(host, SD_CONFIG_CR);



	au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));

	au_sync();

	__raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));

	wmb(); /* drain writebuffer */



	/* Wait for the command to go on the line */

	while (au_readl(HOST_CMD(host)) & SD_CMD_GO)

	while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)

		/* nop */;



	/* Wait for the command to come back */

	if (wait) {

		u32 status = au_readl(HOST_STATUS(host));

		u32 status = __raw_readl(HOST_STATUS(host));



		while (!(status & SD_STATUS_CR))

			status = au_readl(HOST_STATUS(host));

			status = __raw_readl(HOST_STATUS(host));



		/* Clear the CR status */

		au_writel(SD_STATUS_CR, HOST_STATUS(host));

		__raw_writel(SD_STATUS_CR, HOST_STATUS(host));



		IRQ_ON(host, SD_CONFIG_CR);

	}
@@ -339,11 +341,11 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 
	data = mrq->cmd->data;



	if (status == 0)

		status = au_readl(HOST_STATUS(host));

		status = __raw_readl(HOST_STATUS(host));



	/* The transaction is really over when the SD_STATUS_DB bit is clear */

	while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))

		status = au_readl(HOST_STATUS(host));

		status = __raw_readl(HOST_STATUS(host));



	data->error = 0;

	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
@@ -357,7 +359,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) 
		data->error = -EILSEQ;



	/* Clear the CRC bits */

	au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));

	__raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));



	data->bytes_xfered = 0;
@@ -380,7 +382,7 @@ static void au1xmmc_tasklet_data(unsigned long param) 
{

	struct au1xmmc_host *host = (struct au1xmmc_host *)param;



	u32 status = au_readl(HOST_STATUS(host));

	u32 status = __raw_readl(HOST_STATUS(host));

	au1xmmc_data_complete(host, status);

}
@@ -412,15 +414,15 @@ static void au1xmmc_send_pio(struct au1xmmc_host *host) 
		max = AU1XMMC_MAX_TRANSFER;



	for (count = 0; count < max; count++) {

		status = au_readl(HOST_STATUS(host));

		status = __raw_readl(HOST_STATUS(host));



		if (!(status & SD_STATUS_TH))

			break;



		val = *sg_ptr++;



		au_writel((unsigned long)val, HOST_TXPORT(host));

		au_sync();

		__raw_writel((unsigned long)val, HOST_TXPORT(host));

		wmb(); /* drain writebuffer */

	}



	host->pio.len -= count;
@@ -472,7 +474,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) 
		max = AU1XMMC_MAX_TRANSFER;



	for (count = 0; count < max; count++) {

		status = au_readl(HOST_STATUS(host));

		status = __raw_readl(HOST_STATUS(host));



		if (!(status & SD_STATUS_NE))

			break;
@@ -494,7 +496,7 @@ static void au1xmmc_receive_pio(struct au1xmmc_host *host) 
			break;

		}



		val = au_readl(HOST_RXPORT(host));

		val = __raw_readl(HOST_RXPORT(host));



		if (sg_ptr)

			*sg_ptr++ = (unsigned char)(val & 0xFF);
@@ -537,10 +539,10 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 


	if (cmd->flags & MMC_RSP_PRESENT) {

		if (cmd->flags & MMC_RSP_136) {

			r[0] = au_readl(host->iobase + SD_RESP3);

			r[1] = au_readl(host->iobase + SD_RESP2);

			r[2] = au_readl(host->iobase + SD_RESP1);

			r[3] = au_readl(host->iobase + SD_RESP0);

			r[0] = __raw_readl(host->iobase + SD_RESP3);

			r[1] = __raw_readl(host->iobase + SD_RESP2);

			r[2] = __raw_readl(host->iobase + SD_RESP1);

			r[3] = __raw_readl(host->iobase + SD_RESP0);



			/* The CRC is omitted from the response, so really

			 * we only got 120 bytes, but the engine expects
@@ -559,7 +561,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 
			 * that means that the OSR data starts at bit 31,

			 * so we can just read RESP0 and return that.

			 */

			cmd->resp[0] = au_readl(host->iobase + SD_RESP0);

			cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);

		}

	}
@@ -586,7 +588,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) 
			u32 mask = SD_STATUS_DB | SD_STATUS_NE;



			while((status & mask) != mask)

				status = au_readl(HOST_STATUS(host));

				status = __raw_readl(HOST_STATUS(host));

		}



		au1xxx_dbdma_start(channel);
@@ -606,13 +608,13 @@ static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate) 
	pbus /= 2;

	divisor = ((pbus / rate) / 2) - 1;



	config = au_readl(HOST_CONFIG(host));

	config = __raw_readl(HOST_CONFIG(host));



	config &= ~(SD_CONFIG_DIV);

	config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;



	au_writel(config, HOST_CONFIG(host));

	au_sync();

	__raw_writel(config, HOST_CONFIG(host));

	wmb(); /* drain writebuffer */

}



static int au1xmmc_prepare_data(struct au1xmmc_host *host,
@@ -636,7 +638,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host, 
	if (host->dma.len == 0)

		return -ETIMEDOUT;



	au_writel(data->blksz - 1, HOST_BLKSIZE(host));

	__raw_writel(data->blksz - 1, HOST_BLKSIZE(host));



	if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {

		int i;
@@ -723,31 +725,34 @@ static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq) 
static void au1xmmc_reset_controller(struct au1xmmc_host *host)

{

	/* Apply the clock */

	au_writel(SD_ENABLE_CE, HOST_ENABLE(host));

        au_sync_delay(1);

	__raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));

	wmb(); /* drain writebuffer */

	mdelay(1);



	au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));

	au_sync_delay(5);

	__raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));

	wmb(); /* drain writebuffer */

	mdelay(5);



	au_writel(~0, HOST_STATUS(host));

	au_sync();

	__raw_writel(~0, HOST_STATUS(host));

	wmb(); /* drain writebuffer */



	au_writel(0, HOST_BLKSIZE(host));

	au_writel(0x001fffff, HOST_TIMEOUT(host));

	au_sync();

	__raw_writel(0, HOST_BLKSIZE(host));

	__raw_writel(0x001fffff, HOST_TIMEOUT(host));

	wmb(); /* drain writebuffer */



	au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));

        au_sync();

	__raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */



	au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));

	au_sync_delay(1);

	__raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */

	mdelay(1);



	au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));

	au_sync();

	__raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */



	/* Configure interrupts */

	au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));

	au_sync();

	__raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));

	wmb(); /* drain writebuffer */

}
@@ -767,7 +772,7 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
		host->clock = ios->clock;

	}



	config2 = au_readl(HOST_CONFIG2(host));

	config2 = __raw_readl(HOST_CONFIG2(host));

	switch (ios->bus_width) {

	case MMC_BUS_WIDTH_8:

		config2 |= SD_CONFIG2_BB;
@@ -780,8 +785,8 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
		config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);

		break;

	}

	au_writel(config2, HOST_CONFIG2(host));

	au_sync();

	__raw_writel(config2, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */

}



#define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
@@ -793,7 +798,7 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 
	struct au1xmmc_host *host = dev_id;

	u32 status;



	status = au_readl(HOST_STATUS(host));

	status = __raw_readl(HOST_STATUS(host));



	if (!(status & SD_STATUS_I))

		return IRQ_NONE;	/* not ours */
@@ -839,8 +844,8 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) 
				status);

	}



	au_writel(status, HOST_STATUS(host));

	au_sync();

	__raw_writel(status, HOST_STATUS(host));

	wmb(); /* drain writebuffer */



	return IRQ_HANDLED;

}
@@ -976,7 +981,7 @@ static int au1xmmc_probe(struct platform_device *pdev) 
		goto out1;

	}



	host->iobase = (unsigned long)ioremap(r->start, 0x3c);

	host->iobase = ioremap(r->start, 0x3c);

	if (!host->iobase) {

		dev_err(&pdev->dev, "cannot remap mmio\n");

		goto out2;
@@ -1075,7 +1080,7 @@ static int au1xmmc_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, host);



	pr_info(DRIVER_NAME ": MMC Controller %d set up at %8.8X"

	pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"

		" (mode=%s)\n", pdev->id, host->iobase,

		host->flags & HOST_F_DMA ? "dma" : "pio");
@@ -1087,10 +1092,10 @@ static int au1xmmc_probe(struct platform_device *pdev) 
		led_classdev_unregister(host->platdata->led);

out5:

#endif

	au_writel(0, HOST_ENABLE(host));

	au_writel(0, HOST_CONFIG(host));

	au_writel(0, HOST_CONFIG2(host));

	au_sync();

	__raw_writel(0, HOST_ENABLE(host));

	__raw_writel(0, HOST_CONFIG(host));

	__raw_writel(0, HOST_CONFIG2(host));

	wmb(); /* drain writebuffer */



	if (host->flags & HOST_F_DBDMA)

		au1xmmc_dbdma_shutdown(host);
@@ -1130,10 +1135,10 @@ static int au1xmmc_remove(struct platform_device *pdev) 
		    !(host->mmc->caps & MMC_CAP_NEEDS_POLL))

			host->platdata->cd_setup(host->mmc, 0);



		au_writel(0, HOST_ENABLE(host));

		au_writel(0, HOST_CONFIG(host));

		au_writel(0, HOST_CONFIG2(host));

		au_sync();

		__raw_writel(0, HOST_ENABLE(host));

		__raw_writel(0, HOST_CONFIG(host));

		__raw_writel(0, HOST_CONFIG2(host));

		wmb(); /* drain writebuffer */



		tasklet_kill(&host->data_task);

		tasklet_kill(&host->finish_task);
@@ -1158,11 +1163,11 @@ static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state) 
{

	struct au1xmmc_host *host = platform_get_drvdata(pdev);



	au_writel(0, HOST_CONFIG2(host));

	au_writel(0, HOST_CONFIG(host));

	au_writel(0xffffffff, HOST_STATUS(host));

	au_writel(0, HOST_ENABLE(host));

	au_sync();

	__raw_writel(0, HOST_CONFIG2(host));

	__raw_writel(0, HOST_CONFIG(host));

	__raw_writel(0xffffffff, HOST_STATUS(host));

	__raw_writel(0, HOST_ENABLE(host));

	wmb(); /* drain writebuffer */



	return 0;

}