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Commit 2f6f3136 authored by James Hogan's avatar James Hogan Committed by Ralf Baechle
Browse files

MIPS: cpu-features: Add cpu_has_ftlb 



Add cpu_has_ftlb, which specifies that an FTLB is present in addition to
the VTLB, probed based on whether Config.MT == 4 (rather than 1 for
standard JTLB).

This is necessary since MIPS release 6 removes Config4.MMUExtDef, so the
presence of the FTLB fields in Config4 must be determined from Config.MT
instead.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11159/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 19446da4

arch/mips/include/asm/cpu-features.h

+3 −0
Original line number Diff line number Diff line
@@ -20,6 +20,9 @@ 
#ifndef cpu_has_tlb

#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)

#endif

#ifndef cpu_has_ftlb

#define cpu_has_ftlb		(cpu_data[0].options & MIPS_CPU_FTLB)

#endif

#ifndef cpu_has_tlbinv

#define cpu_has_tlbinv		(cpu_data[0].options & MIPS_CPU_TLBINV)

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -385,6 +385,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_CDMM		0x4000000000ull	/* CPU has Common Device Memory Map */

#define MIPS_CPU_BP_GHIST	0x8000000000ull /* R12K+ Branch Prediction Global History */

#define MIPS_CPU_SP		0x10000000000ull /* Small (1KB) page support */

#define MIPS_CPU_FTLB		0x20000000000ull /* CPU has Fixed-page-size TLB */



/*

 * CPU ASE encodings

arch/mips/include/asm/mipsregs.h

+2 −0
Original line number Diff line number Diff line
@@ -487,6 +487,8 @@ 


/* Bits specific to the MIPS32/64 PRA.	*/

#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)

#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)

#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)

#define MIPS_CONF_AR		(_ULCAST_(7) << 10)

#define MIPS_CONF_AT		(_ULCAST_(3) << 13)

#define MIPS_CONF_M		(_ULCAST_(1) << 31)

arch/mips/kernel/cpu-probe.c

+5 −3
Original line number Diff line number Diff line
@@ -410,16 +410,18 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) 
static inline unsigned int decode_config0(struct cpuinfo_mips *c)

{

	unsigned int config0;

	int isa;

	int isa, mt;



	config0 = read_c0_config();



	/*

	 * Look for Standard TLB or Dual VTLB and FTLB

	 */

	if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||

	    (((config0 & MIPS_CONF_MT) >> 7) == 4))

	mt = config0 & MIPS_CONF_MT;

	if (mt == MIPS_CONF_MT_TLB)

		c->options |= MIPS_CPU_TLB;

	else if (mt == MIPS_CONF_MT_FTLB)

		c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;



	isa = (config0 & MIPS_CONF_AT) >> 13;

	switch (isa) {