Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2f2b7fb2 authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: tegra: define DT bindings for and instantiate timer 



The Tegra timer provides a number of 29-bit timer channels, a single
32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules.
The first two channels may also trigger a legacy watchdog reset.

Define a DT binding for this HW module, and add the module into the Tegra
device tree files.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent 9a2ab3f1

Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt

0 → 100644
+21 −0
Original line number Diff line number Diff line 
NVIDIA Tegra20 timer



The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free

running counter. The first two channels may also trigger a watchdog reset.



Required properties:



- compatible : should be "nvidia,tegra20-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 4 interrupts; one per timer channel.



Example:



timer {

	compatible = "nvidia,tegra20-timer";

	reg = <0x60005000 0x60>;

	interrupts = <0 0 0x04

			0 1 0x04

			0 41 0x04

			0 42 0x04>;

};

Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt

0 → 100644
+23 −0
Original line number Diff line number Diff line 
NVIDIA Tegra30 timer



The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free

running counter, and 5 watchdog modules. The first two channels may also

trigger a legacy watchdog reset.



Required properties:



- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".

- reg : Specifies base physical address and size of the registers.

- interrupts : A list of 6 interrupts; one per each of timer channels 1

    through 5, and one for the shared interrupt for the remaining channels.



timer {

	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

	reg = <0x60005000 0x400>;

	interrupts = <0 0 0x04

		      0 1 0x04

		      0 41 0x04

		      0 42 0x04

		      0 121 0x04

		      0 122 0x04>;

};

arch/arm/boot/dts/tegra20.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -108,6 +108,15 @@ 
		#interrupt-cells = <3>;

	};



	timer@60005000 {

		compatible = "nvidia,tegra20-timer";

		reg = <0x60005000 0x60>;

		interrupts = <0 0 0x04

			      0 1 0x04

			      0 41 0x04

			      0 42 0x04>;

	};



	apbdma: dma {

		compatible = "nvidia,tegra20-apbdma";

		reg = <0x6000a000 0x1200>;

arch/arm/boot/dts/tegra30.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -108,6 +108,17 @@ 
		#interrupt-cells = <3>;

	};



	timer@60005000 {

		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";

		reg = <0x60005000 0x400>;

		interrupts = <0 0 0x04

			      0 1 0x04

			      0 41 0x04

			      0 42 0x04

			      0 121 0x04

			      0 122 0x04>;

	};



	apbdma: dma {

		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";

		reg = <0x6000a000 0x1400>;