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Commit 2f24e989 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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drm/msm/dsi-staging: alter phy configurations to support SDM845 



Alter phy configurations for DB mode enabling and lane map settings to
support SDM845. Alter clock name from core clk to escape clk

Change-Id: Ia0356012f83ecef2017d57cffc7ed994e975a8a0
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 4302e8f1

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+1 −1
Original line number Diff line number Diff line
@@ -556,7 +556,7 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, 
		goto fail;

	}



	link->esc_clk = devm_clk_get(&pdev->dev, "core_clk");

	link->esc_clk = devm_clk_get(&pdev->dev, "esc_clk");

	if (IS_ERR(link->esc_clk)) {

		rc = PTR_ERR(link->esc_clk);

		pr_err("failed to get esc_clk, rc=%d\n", rc);

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+2 −2
Original line number Diff line number Diff line
@@ -320,8 +320,8 @@ void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl, 
	reg |= (common_cfg->bit_swap_green ? BIT(4) : 0);

	reg |= (common_cfg->bit_swap_blue ? BIT(8) : 0);

	DSI_W32(ctrl, DSI_VIDEO_MODE_DATA_CTRL, reg);

	/* Enable Timing double buffering */

	DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x1);

	/* Disable Timing double buffering */

	DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);





	pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index);

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+1 −1
Original line number Diff line number Diff line
@@ -388,7 +388,7 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) 
	/** TODO: initialize debugfs */

	dsi_phy->pdev = pdev;

	platform_set_drvdata(pdev, dsi_phy);

	pr_debug("Probe successful for %s\n", dsi_phy->name);

	pr_info("Probe successful for %s\n", dsi_phy->name);

	return 0;



fail_supplies:

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c

+5 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct dsi_phy_hw *phy, 
			    struct dsi_phy_cfg *cfg)

{

	int i;

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x02, 0x01};

	u8 tx_dctrl[] = {0x00, 0x00, 0x00, 0x04, 0x01};



	/* Strength ctrl settings */

	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
@@ -186,6 +186,10 @@ static void dsi_phy_hw_v3_0_lane_settings(struct dsi_phy_hw *phy, 
		DSI_W32(phy, DSIPHY_LNX_OFFSET_BOT_CTRL(i), 0x0);

		DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]);

	}



	/* Toggle BIT 0 to release freeze I/0 */

	DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(3), 0x05);

	DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(3), 0x04);

}



/**