Loading include/asm-mips/cacheops.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -64,7 +64,7 @@ #define Page_Invalidate_T 0x16 #define Page_Invalidate_T 0x16 /* /* * R1000-specific cacheops * R10000-specific cacheops * * * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. Loading Loading
include/asm-mips/cacheops.h +1 −1 Original line number Original line Diff line number Diff line Loading @@ -64,7 +64,7 @@ #define Page_Invalidate_T 0x16 #define Page_Invalidate_T 0x16 /* /* * R1000-specific cacheops * R10000-specific cacheops * * * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. Loading
Ralf Baechle <ralf@linux-mips.org>Ralf Baechle <ralf@linux-mips.org>