Loading Documentation/devicetree/bindings/clock/qcom,gcc.txt +1 −0 Original line number Original line Diff line number Diff line Loading @@ -18,6 +18,7 @@ Required properties : "qcom,gcc-mdm9615" "qcom,gcc-mdm9615" "qcom,gcc-sdm845" "qcom,gcc-sdm845" "qcom,gcc-sdm845-v2" "qcom,gcc-sdm845-v2" "qcom,gcc-sdm845-v2.1" "qcom,gcc-sdm670" "qcom,gcc-sdm670" "qcom,debugcc-sdm845" "qcom,debugcc-sdm845" Loading arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi +4 −0 Original line number Original line Diff line number Diff line Loading @@ -21,3 +21,7 @@ &spmi_bus { &spmi_bus { /delete-property/ qcom,enable-ahb-bus-workaround; /delete-property/ qcom,enable-ahb-bus-workaround; }; }; &clock_gcc { compatible = "qcom,gcc-sdm845-v2.1", "syscon"; }; drivers/clk/qcom/gcc-sdm845.c +5 −3 Original line number Original line Diff line number Diff line Loading @@ -4068,6 +4068,7 @@ static const struct qcom_cc_desc gcc_sdm845_desc = { static const struct of_device_id gcc_sdm845_match_table[] = { static const struct of_device_id gcc_sdm845_match_table[] = { { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-sdm845-v2" }, { .compatible = "qcom,gcc-sdm845-v2" }, { .compatible = "qcom,gcc-sdm845-v2.1" }, { .compatible = "qcom,gcc-sdm670" }, { .compatible = "qcom,gcc-sdm670" }, { } { } }; }; Loading Loading @@ -4267,7 +4268,8 @@ static int gcc_sdm845_fixup(struct platform_device *pdev) if (!compat || (compatlen <= 0)) if (!compat || (compatlen <= 0)) return -EINVAL; return -EINVAL; if (!strcmp(compat, "qcom,gcc-sdm845-v2")) if (!strcmp(compat, "qcom,gcc-sdm845-v2") || !strcmp(compat, "qcom,gcc-sdm845-v2.1")) gcc_sdm845_fixup_sdm845v2(); gcc_sdm845_fixup_sdm845v2(); else if (!strcmp(compat, "qcom,gcc-sdm670")) else if (!strcmp(compat, "qcom,gcc-sdm670")) gcc_sdm845_fixup_sdm670(); gcc_sdm845_fixup_sdm670(); Loading Loading @@ -4322,8 +4324,8 @@ static int gcc_sdm845_probe(struct platform_device *pdev) regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); /* Keep this clock on all the time on SDM845 v1 */ /* Keep this clock on all the times except on SDM845 v2.1 */ if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845")) if (!of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845-v2.1")) clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); /* DFS clock registration */ /* DFS clock registration */ Loading Loading
Documentation/devicetree/bindings/clock/qcom,gcc.txt +1 −0 Original line number Original line Diff line number Diff line Loading @@ -18,6 +18,7 @@ Required properties : "qcom,gcc-mdm9615" "qcom,gcc-mdm9615" "qcom,gcc-sdm845" "qcom,gcc-sdm845" "qcom,gcc-sdm845-v2" "qcom,gcc-sdm845-v2" "qcom,gcc-sdm845-v2.1" "qcom,gcc-sdm670" "qcom,gcc-sdm670" "qcom,debugcc-sdm845" "qcom,debugcc-sdm845" Loading
arch/arm64/boot/dts/qcom/sdm845-v2.1.dtsi +4 −0 Original line number Original line Diff line number Diff line Loading @@ -21,3 +21,7 @@ &spmi_bus { &spmi_bus { /delete-property/ qcom,enable-ahb-bus-workaround; /delete-property/ qcom,enable-ahb-bus-workaround; }; }; &clock_gcc { compatible = "qcom,gcc-sdm845-v2.1", "syscon"; };
drivers/clk/qcom/gcc-sdm845.c +5 −3 Original line number Original line Diff line number Diff line Loading @@ -4068,6 +4068,7 @@ static const struct qcom_cc_desc gcc_sdm845_desc = { static const struct of_device_id gcc_sdm845_match_table[] = { static const struct of_device_id gcc_sdm845_match_table[] = { { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-sdm845" }, { .compatible = "qcom,gcc-sdm845-v2" }, { .compatible = "qcom,gcc-sdm845-v2" }, { .compatible = "qcom,gcc-sdm845-v2.1" }, { .compatible = "qcom,gcc-sdm670" }, { .compatible = "qcom,gcc-sdm670" }, { } { } }; }; Loading Loading @@ -4267,7 +4268,8 @@ static int gcc_sdm845_fixup(struct platform_device *pdev) if (!compat || (compatlen <= 0)) if (!compat || (compatlen <= 0)) return -EINVAL; return -EINVAL; if (!strcmp(compat, "qcom,gcc-sdm845-v2")) if (!strcmp(compat, "qcom,gcc-sdm845-v2") || !strcmp(compat, "qcom,gcc-sdm845-v2.1")) gcc_sdm845_fixup_sdm845v2(); gcc_sdm845_fixup_sdm845v2(); else if (!strcmp(compat, "qcom,gcc-sdm670")) else if (!strcmp(compat, "qcom,gcc-sdm670")) gcc_sdm845_fixup_sdm670(); gcc_sdm845_fixup_sdm670(); Loading Loading @@ -4322,8 +4324,8 @@ static int gcc_sdm845_probe(struct platform_device *pdev) regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); /* Keep this clock on all the time on SDM845 v1 */ /* Keep this clock on all the times except on SDM845 v2.1 */ if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845")) if (!of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-sdm845-v2.1")) clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); clk_prepare_enable(gcc_aggre_noc_pcie_tbu_clk.clkr.hw.clk); /* DFS clock registration */ /* DFS clock registration */ Loading