Loading Documentation/ABI/testing/sysfs-platform-i2c-demux-pinctrl +12 −17 Original line number Diff line number Diff line What: /sys/devices/platform/<i2c-demux-name>/cur_master What: /sys/devices/platform/<i2c-demux-name>/available_masters Date: January 2016 KernelVersion: 4.6 Contact: Wolfram Sang <wsa@the-dreams.de> Description: Reading the file will give you a list of masters which can be selected for a demultiplexed bus. The format is "<index>:<name>". Example from a Renesas Lager board: This file selects the active I2C master for a demultiplexed bus. 0:/i2c@e6500000 1:/i2c@e6508000 Write 0 there for the first master, 1 for the second etc. Reading the file will give you a list with the active master marked. Example from a Renesas Lager board: root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master * 0 - /i2c@9 1 - /i2c@e6520000 2 - /i2c@e6530000 root@Lager:~# echo 2 > /sys/devices/platform/i2c@8/cur_master root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master 0 - /i2c@9 1 - /i2c@e6520000 * 2 - /i2c@e6530000 What: /sys/devices/platform/<i2c-demux-name>/current_master Date: January 2016 KernelVersion: 4.6 Contact: Wolfram Sang <wsa@the-dreams.de> Description: This file selects/shows the active I2C master for a demultiplexed bus. It uses the <index> value from the file 'available_masters'. Documentation/devicetree/bindings/clock/qca,ath79-pll.txt +3 −3 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. Required Properties: - compatible: has to be "qca,<soctype>-cpu-intc" and one of the following - compatible: has to be "qca,<soctype>-pll" and one of the following fallbacks: - "qca,ar7100-pll" - "qca,ar7240-pll" Loading @@ -21,8 +21,8 @@ Optional properties: Example: memory-controller@18050000 { compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; pll-controller@18050000 { compatible = "qca,ar9132-pll", "qca,ar9130-pll"; reg = <0x18050000 0x20>; clock-names = "ref"; Loading Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; }; Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +14 −8 Original line number Diff line number Diff line Loading @@ -3,17 +3,23 @@ Rockchip EMMC PHY Required properties: - compatible: rockchip,rk3399-emmc-phy - rockchip,grf : phandle to the syscon managing the "general register files" - #phy-cells: must be 0 - reg: PHY configure reg address offset in "general - reg: PHY register address offset and length in "general register files" Example: emmcphy: phy { grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; ... emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; rockchip,grf = <&grf>; reg = <0xf780>; reg = <0xf780 0x20>; #phy-cells = <0>; }; }; Loading
Documentation/ABI/testing/sysfs-platform-i2c-demux-pinctrl +12 −17 Original line number Diff line number Diff line What: /sys/devices/platform/<i2c-demux-name>/cur_master What: /sys/devices/platform/<i2c-demux-name>/available_masters Date: January 2016 KernelVersion: 4.6 Contact: Wolfram Sang <wsa@the-dreams.de> Description: Reading the file will give you a list of masters which can be selected for a demultiplexed bus. The format is "<index>:<name>". Example from a Renesas Lager board: This file selects the active I2C master for a demultiplexed bus. 0:/i2c@e6500000 1:/i2c@e6508000 Write 0 there for the first master, 1 for the second etc. Reading the file will give you a list with the active master marked. Example from a Renesas Lager board: root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master * 0 - /i2c@9 1 - /i2c@e6520000 2 - /i2c@e6530000 root@Lager:~# echo 2 > /sys/devices/platform/i2c@8/cur_master root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master 0 - /i2c@9 1 - /i2c@e6520000 * 2 - /i2c@e6530000 What: /sys/devices/platform/<i2c-demux-name>/current_master Date: January 2016 KernelVersion: 4.6 Contact: Wolfram Sang <wsa@the-dreams.de> Description: This file selects/shows the active I2C master for a demultiplexed bus. It uses the <index> value from the file 'available_masters'.
Documentation/devicetree/bindings/clock/qca,ath79-pll.txt +3 −3 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. Required Properties: - compatible: has to be "qca,<soctype>-cpu-intc" and one of the following - compatible: has to be "qca,<soctype>-pll" and one of the following fallbacks: - "qca,ar7100-pll" - "qca,ar7240-pll" Loading @@ -21,8 +21,8 @@ Optional properties: Example: memory-controller@18050000 { compatible = "qca,ar9132-ppl", "qca,ar9130-pll"; pll-controller@18050000 { compatible = "qca,ar9132-pll", "qca,ar9130-pll"; reg = <0x18050000 0x20>; clock-names = "ref"; Loading
Documentation/devicetree/bindings/net/mediatek-net.txt +5 −2 Original line number Diff line number Diff line Loading @@ -9,7 +9,8 @@ have dual GMAC each represented by a child node.. Required properties: - compatible: Should be "mediatek,mt7623-eth" - reg: Address and length of the register set for the device - interrupts: Should contain the frame engines interrupt - interrupts: Should contain the three frame engines interrupts in numeric order. These are fe_int0, fe_int1 and fe_int2. - clocks: the clock used by the core - clock-names: the names of the clock listed in the clocks property. These are "ethif", "esw", "gp2", "gp1" Loading Loading @@ -42,7 +43,9 @@ eth: ethernet@1b100000 { <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; Loading
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +11 −7 Original line number Diff line number Diff line Loading @@ -8,15 +8,19 @@ Required properties: of memory mapped region. - clock-names: from common clock binding: Required elements: "24m" - rockchip,grf: phandle to the syscon managing the "general register files" - #phy-cells : from the generic PHY bindings, must be 0; Example: grf: syscon@ff770000 { compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; ... edp_phy: edp-phy { compatible = "rockchip,rk3288-dp-phy"; rockchip,grf = <&grf>; clocks = <&cru SCLK_EDP_24M>; clock-names = "24m"; #phy-cells = <0>; }; };
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt +14 −8 Original line number Diff line number Diff line Loading @@ -3,17 +3,23 @@ Rockchip EMMC PHY Required properties: - compatible: rockchip,rk3399-emmc-phy - rockchip,grf : phandle to the syscon managing the "general register files" - #phy-cells: must be 0 - reg: PHY configure reg address offset in "general - reg: PHY register address offset and length in "general register files" Example: emmcphy: phy { grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; #address-cells = <1>; #size-cells = <1>; ... emmcphy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; rockchip,grf = <&grf>; reg = <0xf780>; reg = <0xf780 0x20>; #phy-cells = <0>; }; };
