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Commit 2d3ed34e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: add support to configure dsi clock"

parents 6fe8bff4 812bd723

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c

+7 −3
Original line number Diff line number Diff line
@@ -785,10 +785,14 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, 
	if (host_cfg->data_lanes & DSI_DATA_LANE_3)

		num_of_lanes++;



	if (config->bit_clk_rate_hz == 0) {

		h_period = DSI_H_TOTAL_DSC(timing);

		v_period = DSI_V_TOTAL(timing);



		bit_rate = h_period * v_period * timing->refresh_rate * bpp * 8;

	} else {

		bit_rate = config->bit_clk_rate_hz * num_of_lanes;

	}



	bit_rate_per_lane = bit_rate;

	do_div(bit_rate_per_lane, num_of_lanes);

	pclk_rate = bit_rate;

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+4 −1
Original line number Diff line number Diff line
@@ -355,6 +355,7 @@ struct dsi_panel_cmd_set { 
 * @v_front_porch:    Vertical front porch in lines.

 * @v_sync_polarity:  Polarity of VSYNC (false is active low).

 * @refresh_rate:     Refresh rate in Hz.

 * @clk_rate_hz:      DSI bit clock rate per lane in Hz.

 * @dsc_enabled:      DSC compression enabled.

 * @dsc:              DSC compression configuration.

 */
@@ -373,7 +374,7 @@ struct dsi_mode_info { 
	bool v_sync_polarity;



	u32 refresh_rate;



	u64 clk_rate_hz;

	bool dsc_enabled;

	struct msm_display_dsc_info *dsc;

};
@@ -500,6 +501,7 @@ struct dsi_host_config { 
 * @phy_timing_len:       Phy timing array length

 * @panel_jitter:         Panel jitter for RSC backoff

 * @panel_prefill_lines:  Panel prefill lines for RSC

 * @clk_rate_hz:          DSI bit clock per lane in hz.

 * @topology:             Topology selected for the panel

 * @dsc:                  DSC compression info

 * @dsc_enabled:          DSC compression enabled
@@ -513,6 +515,7 @@ struct dsi_display_mode_priv_info { 
	u32 panel_jitter_numer;

	u32 panel_jitter_denom;

	u32 panel_prefill_lines;

	u64 clk_rate_hz;



	struct msm_display_topology topology;

	struct msm_display_dsc_info dsc;

drivers/gpu/drm/msm/dsi-staging/dsi_drm.c

+1 −0
Original line number Diff line number Diff line
@@ -318,6 +318,7 @@ int dsi_conn_get_mode_info(const struct drm_display_mode *drm_mode, 
	mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;

	mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;

	mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;

	mode_info->clk_rate = dsi_mode.priv_info->clk_rate_hz;



	memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,

			sizeof(struct msm_display_topology));

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+16 −0
Original line number Diff line number Diff line
@@ -683,6 +683,21 @@ static int dsi_panel_parse_timing(struct dsi_mode_info *mode, 
				  struct device_node *of_node)

{

	int rc = 0;

	u64 tmp64;

	struct dsi_display_mode *display_mode;



	display_mode = container_of(mode, struct dsi_display_mode, timing);



	rc = of_property_read_u64(of_node,

			"qcom,mdss-dsi-panel-clockrate", &tmp64);

	if (rc == -EOVERFLOW) {

		tmp64 = 0;

		rc = of_property_read_u32(of_node,

			"qcom,mdss-dsi-panel-clockrate", (u32 *)&tmp64);

	}



	mode->clk_rate_hz = !rc ? tmp64 : 0;

	display_mode->priv_info->clk_rate_hz = mode->clk_rate_hz;



	rc = of_property_read_u32(of_node, "qcom,mdss-dsi-panel-framerate",

				  &mode->refresh_rate);
@@ -3074,6 +3089,7 @@ int dsi_panel_get_host_cfg_for_mode(struct dsi_panel *panel, 
	config->video_timing.dsc_enabled = mode->priv_info->dsc_enabled;

	config->video_timing.dsc = &mode->priv_info->dsc;



	config->bit_clk_rate_hz = mode->priv_info->clk_rate_hz;

	config->esc_clk_rate_hz = 19200000;

	mutex_unlock(&panel->panel_lock);

	return rc;

drivers/gpu/drm/msm/msm_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -406,6 +406,7 @@ struct msm_display_topology { 
 * @prefill_lines:   prefill lines based on porches.

 * @jitter_numer:	display panel jitter numerator configuration

 * @jitter_denom:	display panel jitter denominator configuration

 * @clk_rate:	     DSI bit clock per lane in HZ.

 * @topology:        supported topology for the mode

 * @comp_info:       compression info supported

 */
@@ -415,6 +416,7 @@ struct msm_mode_info { 
	uint32_t prefill_lines;

	uint32_t jitter_numer;

	uint32_t jitter_denom;

	uint64_t clk_rate;

	struct msm_display_topology topology;

	struct msm_compression_info comp_info;

};
@@ -433,6 +435,7 @@ struct msm_mode_info { 
 *                      this is max width supported by controller

 * @max_height:         Max height of display. In case of hot pluggable display

 *                      this is max height supported by controller

 * @clk_rate:           DSI bit clock per lane in HZ.

 * @is_primary:         Set to true if display is primary display

 * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is

 *				 used instead of panel TE in cmd mode panels
@@ -452,6 +455,7 @@ struct msm_display_info { 


	uint32_t max_width;

	uint32_t max_height;

	uint64_t clk_rate;



	bool is_primary;

	bool is_te_using_watchdog_timer;