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Commit 2d1fe073 authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev) 



dev_priv is what the macro works hard to extract, pass it directly.

> sed 's/\([A-Z].*(dev_priv\)->dev)/\1)/g'

v2:
- Include all wrapper macros too (Chris)

v3:
- Include sed cmdline (Chris)

v4:
- Break long line
- Rebase

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1460016485-8089-1-git-send-email-joonas.lahtinen@linux.intel.com
parent 9458f4ba

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -2415,7 +2415,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data) 
	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;

	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;

	u32 tmp, i;

	u32 tmp, i;





	if (!HAS_GUC_UCODE(dev_priv->dev))

	if (!HAS_GUC_UCODE(dev_priv))

		return 0;

		return 0;





	seq_printf(m, "GuC firmware status:\n");

	seq_printf(m, "GuC firmware status:\n");
@@ -2489,7 +2489,7 @@ static int i915_guc_info(struct seq_file *m, void *data) 
	struct intel_engine_cs *engine;

	struct intel_engine_cs *engine;

	u64 total = 0;

	u64 total = 0;





	if (!HAS_GUC_SCHED(dev_priv->dev))

	if (!HAS_GUC_SCHED(dev_priv))

		return 0;

		return 0;





	if (mutex_lock_interruptible(&dev->struct_mutex))

	if (mutex_lock_interruptible(&dev->struct_mutex))

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1400,7 +1400,7 @@ static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 
	if (err)

	if (err)

		goto err2;

		goto err2;





	if (!IS_CHERRYVIEW(dev_priv->dev))

	if (!IS_CHERRYVIEW(dev_priv))

		vlv_save_gunit_s0ix_state(dev_priv);

		vlv_save_gunit_s0ix_state(dev_priv);





	err = vlv_force_gfx_clock(dev_priv, false);

	err = vlv_force_gfx_clock(dev_priv, false);
@@ -1432,7 +1432,7 @@ static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 
	 */

	 */

	ret = vlv_force_gfx_clock(dev_priv, true);

	ret = vlv_force_gfx_clock(dev_priv, true);





	if (!IS_CHERRYVIEW(dev_priv->dev))

	if (!IS_CHERRYVIEW(dev_priv))

		vlv_restore_gunit_s0ix_state(dev_priv);

		vlv_restore_gunit_s0ix_state(dev_priv);





	err = vlv_allow_gt_wake(dev_priv, true);

	err = vlv_allow_gt_wake(dev_priv, true);

drivers/gpu/drm/i915/i915_gem_gtt.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -2306,7 +2306,7 @@ void i915_check_and_clear_faults(struct drm_device *dev) 




static void i915_ggtt_flush(struct drm_i915_private *dev_priv)

static void i915_ggtt_flush(struct drm_i915_private *dev_priv)

{

{

	if (INTEL_INFO(dev_priv->dev)->gen < 6) {

	if (INTEL_INFO(dev_priv)->gen < 6) {

		intel_gtt_chipset_flush();

		intel_gtt_chipset_flush();

	} else {

	} else {

		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);

		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
@@ -2977,7 +2977,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) 
	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |

	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |

	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));

	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));





	if (!USES_PPGTT(dev_priv->dev))

	if (!USES_PPGTT(dev_priv))

		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,

		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,

		 * so RTL will always use the value corresponding to

		 * so RTL will always use the value corresponding to

		 * pat_sel = 000".

		 * pat_sel = 000".

drivers/gpu/drm/i915/i915_gpu_error.c

+4 −3
Original line number Original line Diff line number Diff line
@@ -669,7 +669,8 @@ i915_error_object_create(struct drm_i915_private *dev_priv, 
	}

	}





	/* Cannot access snooped pages through the aperture */

	/* Cannot access snooped pages through the aperture */

	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))

	if (use_ggtt && src->cache_level != I915_CACHE_NONE &&

	    !HAS_LLC(dev_priv))

		goto unwind;

		goto unwind;





	dst->page_count = num_pages;

	dst->page_count = num_pages;
@@ -884,7 +885,7 @@ static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 
	ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];

	ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];

	ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];

	ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];





	if (HAS_VEBOX(dev_priv->dev)) {

	if (HAS_VEBOX(dev_priv)) {

		ering->semaphore_mboxes[2] =

		ering->semaphore_mboxes[2] =

			I915_READ(RING_SYNC_2(engine->mmio_base));

			I915_READ(RING_SYNC_2(engine->mmio_base));

		ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];

		ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
@@ -1051,7 +1052,7 @@ static void i915_gem_record_rings(struct drm_device *dev, 
							 request->batch_obj,

							 request->batch_obj,

							 vm);

							 vm);





			if (HAS_BROKEN_CS_TLB(dev_priv->dev))

			if (HAS_BROKEN_CS_TLB(dev_priv))

				error->ring[i].wa_batchbuffer =

				error->ring[i].wa_batchbuffer =

					i915_error_ggtt_object_create(dev_priv,

					i915_error_ggtt_object_create(dev_priv,

							     engine->scratch.obj);

							     engine->scratch.obj);

drivers/gpu/drm/i915/i915_irq.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -1218,7 +1218,7 @@ static void ivybridge_parity_work(struct work_struct *work) 
		i915_reg_t reg;

		i915_reg_t reg;





		slice--;

		slice--;

		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))

		if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))

			break;

			break;





		dev_priv->l3_parity.which_slice &= ~(1<<slice);

		dev_priv->l3_parity.which_slice &= ~(1<<slice);
@@ -1257,7 +1257,7 @@ static void ivybridge_parity_work(struct work_struct *work) 
out:

out:

	WARN_ON(dev_priv->l3_parity.which_slice);

	WARN_ON(dev_priv->l3_parity.which_slice);

	spin_lock_irq(&dev_priv->irq_lock);

	spin_lock_irq(&dev_priv->irq_lock);

	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));

	gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));

	spin_unlock_irq(&dev_priv->irq_lock);

	spin_unlock_irq(&dev_priv->irq_lock);





	mutex_unlock(&dev_priv->dev->struct_mutex);

	mutex_unlock(&dev_priv->dev->struct_mutex);
@@ -1626,7 +1626,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 
	if (INTEL_INFO(dev_priv)->gen >= 8)

	if (INTEL_INFO(dev_priv)->gen >= 8)

		return;

		return;





	if (HAS_VEBOX(dev_priv->dev)) {

	if (HAS_VEBOX(dev_priv)) {

		if (pm_iir & PM_VEBOX_USER_INTERRUPT)

		if (pm_iir & PM_VEBOX_USER_INTERRUPT)

			notify_ring(&dev_priv->engine[VECS]);

			notify_ring(&dev_priv->engine[VECS]);
@@ -2828,7 +2828,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr, 
	struct drm_i915_private *dev_priv = engine->dev->dev_private;

	struct drm_i915_private *dev_priv = engine->dev->dev_private;

	struct intel_engine_cs *signaller;

	struct intel_engine_cs *signaller;





	if (INTEL_INFO(dev_priv->dev)->gen >= 8) {

	if (INTEL_INFO(dev_priv)->gen >= 8) {

		for_each_engine(signaller, dev_priv) {

		for_each_engine(signaller, dev_priv) {

			if (engine == signaller)

			if (engine == signaller)

				continue;

				continue;