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Commit 2d112de7 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira Committed by Daniel Vetter
Browse files

drm/i915: Embedded struct drm_crtc_state in intel_crtc_state 



And get rid of the duplicate mode structures. This patch was generated
with the following semantic patch:

@@ @@
struct intel_crtc_state {
+struct drm_crtc_state base;
+
...
-struct drm_display_mode requested_mode;
-struct drm_display_mode adjusted_mode;
...
}
@@ struct intel_crtc_state *state; @@
-state->adjusted_mode
+state->base.adjusted_mode
@@ struct intel_crtc_state *state; @@
-state->requested_mode
+state->base.mode
@@ struct intel_crtc_state state; @@
-state.adjusted_mode
+state.base.adjusted_mode
@@ struct intel_crtc_state state; @@
-state.requested_mode
+state.base.mode
@@ struct drm_crtc *crtc; @@
-to_intel_crtc(crtc)->config.adjusted_mode
+to_intel_crtc(crtc)->config.base.adjusted_mode
@@ identifier member; expression E; @@
-PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E);
+PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E);
@@ identifier member; @@
-PIPE_CONF_CHECK_I(adjusted_mode.member);
+PIPE_CONF_CHECK_I(base.adjusted_mode.member);
@@ identifier member; @@
-PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member);
+PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member);

v2: Completely generate the patch with cocci. (Ander)

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5cec258b

drivers/gpu/drm/i915/i915_irq.c

+4 −4
Original line number Diff line number Diff line
@@ -593,7 +593,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 
		struct intel_crtc *intel_crtc =

			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);

		const struct drm_display_mode *mode =

			&intel_crtc->config.adjusted_mode;

			&intel_crtc->config.base.adjusted_mode;



		htotal = mode->crtc_htotal;

		hsync_start = mode->crtc_hsync_start;
@@ -664,7 +664,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 
{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	const struct drm_display_mode *mode = &crtc->config.adjusted_mode;

	const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;

	enum pipe pipe = crtc->pipe;

	int position, vtotal;
@@ -691,7 +691,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;

	const struct drm_display_mode *mode = &intel_crtc->config.base.adjusted_mode;

	int position;

	int vbl_start, vbl_end, hsync_start, htotal, vtotal;

	bool in_vbl = true;
@@ -849,7 +849,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 
	return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,

						     vblank_time, flags,

						     crtc,

						     &to_intel_crtc(crtc)->config.adjusted_mode);

						     &to_intel_crtc(crtc)->config.base.adjusted_mode);

}



static bool intel_hpd_irq_event(struct drm_device *dev,

drivers/gpu/drm/i915/intel_audio.c

+1 −1
Original line number Diff line number Diff line
@@ -400,7 +400,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 
{

	struct drm_encoder *encoder = &intel_encoder->base;

	struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);

	struct drm_display_mode *mode = &crtc->config.adjusted_mode;

	struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;

	struct drm_connector *connector;

	struct drm_device *dev = encoder->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

drivers/gpu/drm/i915/intel_crt.c

+5 −5
Original line number Diff line number Diff line
@@ -115,14 +115,14 @@ static void intel_crt_get_config(struct intel_encoder *encoder, 
	struct drm_device *dev = encoder->base.dev;

	int dotclock;



	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);

	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);



	dotclock = pipe_config->port_clock;



	if (HAS_PCH_SPLIT(dev))

		ironlake_check_encoder_dotclock(pipe_config, dotclock);



	pipe_config->adjusted_mode.crtc_clock = dotclock;

	pipe_config->base.adjusted_mode.crtc_clock = dotclock;

}



static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -130,11 +130,11 @@ static void hsw_crt_get_config(struct intel_encoder *encoder, 
{

	intel_ddi_get_config(encoder, pipe_config);



	pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

					      DRM_MODE_FLAG_NHSYNC |

					      DRM_MODE_FLAG_PVSYNC |

					      DRM_MODE_FLAG_NVSYNC);

	pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);

	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);

}



static void hsw_crt_pre_enable(struct intel_encoder *encoder)
@@ -157,7 +157,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crt *crt = intel_encoder_to_crt(encoder);

	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;

	struct drm_display_mode *adjusted_mode = &crtc->config.base.adjusted_mode;

	u32 adpa;



	if (INTEL_INFO(dev)->gen >= 5)

drivers/gpu/drm/i915/intel_ddi.c

+9 −9
Original line number Diff line number Diff line
@@ -768,11 +768,11 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder, 
	pipe_config->port_clock = link_clock;



	if (pipe_config->has_dp_encoder)

		pipe_config->adjusted_mode.crtc_clock =

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->dp_m_n);

	else

		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;

		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;

}



static void hsw_ddi_clock_get(struct intel_encoder *encoder,
@@ -820,15 +820,15 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, 
	pipe_config->port_clock = link_clock * 2;



	if (pipe_config->has_pch_encoder)

		pipe_config->adjusted_mode.crtc_clock =

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->fdi_m_n);

	else if (pipe_config->has_dp_encoder)

		pipe_config->adjusted_mode.crtc_clock =

		pipe_config->base.adjusted_mode.crtc_clock =

			intel_dotclock_calculate(pipe_config->port_clock,

						 &pipe_config->dp_m_n);

	else

		pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;

		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;

}



void intel_ddi_clock_get(struct intel_encoder *encoder,
@@ -1261,9 +1261,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 
		BUG();

	}



	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)

	if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)

		temp |= TRANS_DDI_PVSYNC;

	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)

	if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)

		temp |= TRANS_DDI_PHSYNC;



	if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1533,7 +1533,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 


		intel_hdmi->set_infoframes(encoder,

					   crtc->config.has_hdmi_sink,

					   &crtc->config.adjusted_mode);

					   &crtc->config.base.adjusted_mode);

	}

}
@@ -2045,7 +2045,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
	else

		flags |= DRM_MODE_FLAG_NVSYNC;



	pipe_config->adjusted_mode.flags |= flags;

	pipe_config->base.adjusted_mode.flags |= flags;



	switch (temp & TRANS_DDI_BPC_MASK) {

	case TRANS_DDI_BPC_6:

drivers/gpu/drm/i915/intel_display.c

+74 −73
Original line number Diff line number Diff line
@@ -897,7 +897,7 @@ bool intel_crtc_active(struct drm_crtc *crtc) 
	 * properly reconstruct framebuffers.

	 */

	return intel_crtc->active && crtc->primary->fb &&

		intel_crtc->config.adjusted_mode.crtc_clock;

		intel_crtc->config.base.adjusted_mode.crtc_clock;

}



enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -2941,7 +2941,7 @@ static void intel_update_pipe_size(struct intel_crtc *crtc) 
	 * then update the pipesrc and pfit state, even on the flip path.

	 */



	adjusted_mode = &crtc->config.adjusted_mode;

	adjusted_mode = &crtc->config.base.adjusted_mode;



	I915_WRITE(PIPESRC(crtc->pipe),

		   ((adjusted_mode->crtc_hdisplay - 1) << 16) |
@@ -3577,7 +3577,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc) 
{

	struct drm_device *dev = crtc->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;

	int clock = to_intel_crtc(crtc)->config.base.adjusted_mode.crtc_clock;

	u32 divsel, phaseinc, auxdiv, phasedir = 0;

	u32 temp;
@@ -4908,7 +4908,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) 
	for_each_intel_crtc(dev, intel_crtc) {

		if (intel_crtc->new_enabled)

			max_pixclk = max(max_pixclk,

					 intel_crtc->new_config->adjusted_mode.crtc_clock);

					 intel_crtc->new_config->base.adjusted_mode.crtc_clock);

	}



	return max_pixclk;
@@ -5429,7 +5429,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 
				       struct intel_crtc_state *pipe_config)

{

	struct drm_device *dev = intel_crtc->base.dev;

	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;

	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	int lane, link_bw, fdi_dotclock;

	bool setup_ok, needs_recompute = false;
@@ -5484,7 +5484,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, 
{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;

	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;



	/* FIXME should check pixel clock limits on all platforms */

	if (INTEL_INFO(dev)->gen < 4) {
@@ -6206,7 +6206,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 
	enum pipe pipe = intel_crtc->pipe;

	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;

	struct drm_display_mode *adjusted_mode =

		&intel_crtc->config.adjusted_mode;

		&intel_crtc->config.base.adjusted_mode;

	uint32_t crtc_vtotal, crtc_vblank_end;

	int vsyncshift = 0;
@@ -6277,56 +6277,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, 
	uint32_t tmp;



	tmp = I915_READ(HTOTAL(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(HBLANK(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(HSYNC(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;



	tmp = I915_READ(VTOTAL(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(VBLANK(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;

	tmp = I915_READ(VSYNC(cpu_transcoder));

	pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;

	pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;

	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;



	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {

		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;

		pipe_config->adjusted_mode.crtc_vtotal += 1;

		pipe_config->adjusted_mode.crtc_vblank_end += 1;

		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;

		pipe_config->base.adjusted_mode.crtc_vtotal += 1;

		pipe_config->base.adjusted_mode.crtc_vblank_end += 1;

	}



	tmp = I915_READ(PIPESRC(crtc->pipe));

	pipe_config->pipe_src_h = (tmp & 0xffff) + 1;

	pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;



	pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;

	pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;

	pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;

	pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;

}



void intel_mode_from_pipe_config(struct drm_display_mode *mode,

				 struct intel_crtc_state *pipe_config)

{

	mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;

	mode->htotal = pipe_config->adjusted_mode.crtc_htotal;

	mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;

	mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;

	mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;

	mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;

	mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;

	mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;



	mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;

	mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;

	mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;

	mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;

	mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;

	mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;

	mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;

	mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;



	mode->flags = pipe_config->adjusted_mode.flags;

	mode->flags = pipe_config->base.adjusted_mode.flags;



	mode->clock = pipe_config->adjusted_mode.crtc_clock;

	mode->flags |= pipe_config->adjusted_mode.flags;

	mode->clock = pipe_config->base.adjusted_mode.crtc_clock;

	mode->flags |= pipe_config->base.adjusted_mode.flags;

}



static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -6376,7 +6376,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 
		}

	}



	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

	if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {

		if (INTEL_INFO(dev)->gen < 4 ||

		    intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))

			pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -7133,7 +7133,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc) 
	if (intel_crtc->config.dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);



	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

	if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		val |= PIPECONF_INTERLACED_ILK;

	else

		val |= PIPECONF_PROGRESSIVE;
@@ -7223,7 +7223,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc) 
	if (IS_HASWELL(dev) && intel_crtc->config.dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);



	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

	if (intel_crtc->config.base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)

		val |= PIPECONF_INTERLACED_ILK;

	else

		val |= PIPECONF_PROGRESSIVE;
@@ -8789,7 +8789,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc, 
	 * agree once we know their relationship in the encoder's

	 * get_config() function.

	 */

	pipe_config->adjusted_mode.crtc_clock =

	pipe_config->base.adjusted_mode.crtc_clock =

		intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,

					 &pipe_config->fdi_m_n);

}
@@ -9981,10 +9981,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
		      pipe_config->has_infoframe);



	DRM_DEBUG_KMS("requested mode:\n");

	drm_mode_debug_printmodeline(&pipe_config->requested_mode);

	drm_mode_debug_printmodeline(&pipe_config->base.mode);

	DRM_DEBUG_KMS("adjusted mode:\n");

	drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);

	intel_dump_crtc_timings(&pipe_config->adjusted_mode);

	drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);

	intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);

	DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);

	DRM_DEBUG_KMS("pipe src size: %dx%d\n",

		      pipe_config->pipe_src_w, pipe_config->pipe_src_h);
@@ -10108,8 +10108,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	if (!pipe_config)

		return ERR_PTR(-ENOMEM);



	drm_mode_copy(&pipe_config->adjusted_mode, mode);

	drm_mode_copy(&pipe_config->requested_mode, mode);

	drm_mode_copy(&pipe_config->base.adjusted_mode, mode);

	drm_mode_copy(&pipe_config->base.mode, mode);



	pipe_config->cpu_transcoder =

		(enum transcoder) to_intel_crtc(crtc)->pipe;
@@ -10120,13 +10120,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	 * positive or negative polarity is requested, treat this as meaning

	 * negative polarity.

	 */

	if (!(pipe_config->adjusted_mode.flags &

	if (!(pipe_config->base.adjusted_mode.flags &

	      (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))

		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;

		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;



	if (!(pipe_config->adjusted_mode.flags &

	if (!(pipe_config->base.adjusted_mode.flags &

	      (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))

		pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;

		pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;



	/* Compute a starting value for pipe_config->pipe_bpp taking the source

	 * plane pixel format and any sink constraints into account. Returns the
@@ -10145,7 +10145,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	 * computation to clearly distinguish it from the adjusted mode, which

	 * can be changed by the connectors in the below retry loop.

	 */

	drm_crtc_get_hv_timing(&pipe_config->requested_mode,

	drm_crtc_get_hv_timing(&pipe_config->base.mode,

			       &pipe_config->pipe_src_w,

			       &pipe_config->pipe_src_h);
@@ -10155,7 +10155,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	pipe_config->pixel_multiplier = 1;



	/* Fill in default crtc timings, allow encoders to overwrite them. */

	drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);

	drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,

			      CRTC_STEREO_DOUBLE);



	/* Pass our mode to the connectors and the CRTC to give them a chance to

	 * adjust it according to limitations or connector properties, and also
@@ -10175,7 +10176,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc, 
	/* Set default port clock if not overwritten by the encoder. Needs to be

	 * done afterwards in case the encoder adjusts the mode. */

	if (!pipe_config->port_clock)

		pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock

		pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock

			* pipe_config->pixel_multiplier;



	ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -10476,19 +10477,19 @@ intel_pipe_config_compare(struct drm_device *dev, 
		PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);

	}



	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);



	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);

	PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);



	PIPE_CONF_CHECK_I(pixel_multiplier);

	PIPE_CONF_CHECK_I(has_hdmi_sink);
@@ -10499,17 +10500,17 @@ intel_pipe_config_compare(struct drm_device *dev, 


	PIPE_CONF_CHECK_I(has_audio);



	PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,

	PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,

			      DRM_MODE_FLAG_INTERLACE);



	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {

		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,

		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,

				      DRM_MODE_FLAG_PHSYNC);

		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,

		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,

				      DRM_MODE_FLAG_NHSYNC);

		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,

		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,

				      DRM_MODE_FLAG_PVSYNC);

		PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,

		PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,

				      DRM_MODE_FLAG_NVSYNC);

	}
@@ -10559,7 +10560,7 @@ intel_pipe_config_compare(struct drm_device *dev, 
	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)

		PIPE_CONF_CHECK_I(pipe_bpp);



	PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);

	PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);

	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);



#undef PIPE_CONF_CHECK_X
@@ -10835,9 +10836,9 @@ void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, 
	 * FDI already provided one idea for the dotclock.

	 * Yell if the encoder disagrees.

	 */

	WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),

	WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),

	     "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",

	     pipe_config->adjusted_mode.crtc_clock, dotclock);

	     pipe_config->base.adjusted_mode.crtc_clock, dotclock);

}



static void update_scanline_offset(struct intel_crtc *crtc)
@@ -10863,7 +10864,7 @@ static void update_scanline_offset(struct intel_crtc *crtc) 
	 * one to the value.

	 */

	if (IS_GEN2(dev)) {

		const struct drm_display_mode *mode = &crtc->config.adjusted_mode;

		const struct drm_display_mode *mode = &crtc->config.base.adjusted_mode;

		int vtotal;



		vtotal = mode->crtc_vtotal;
@@ -10992,7 +10993,7 @@ static int __intel_set_mode(struct drm_crtc *crtc, 
		 * timestamping. They are derived from true hwmode.

		 */

		drm_calc_timestamping_constants(crtc,

						&pipe_config->adjusted_mode);

						&pipe_config->base.adjusted_mode);

	}



	/* Only after disabling all output pipelines that will be changed can we