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Commit 2ce34b10 authored by Shawn Guo's avatar Shawn Guo
Browse files

Merge tag 'imx-soc-3.19' into imx/dt

The i.MX SoC update for 3.19:
 - Update i.MX6 suspend code to check DDR instead of CPU type, as the
   difference we need to handle is between LPDDR2 and DDR3, not SoCs.
 - Set anatop properly for LPDDR2 in DSM mode
 - Add support for new SoC LS1021A which integrates dual Cortex-A7
 - Add ENET initialization for i.MX6SX platform
 - Add cpufreq support for i.MX53 platform
 - Add a SNVS based poweroff driver for i.MX6 platforms
 - Use ARM  Global Timer as clocksource on VF610

Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve
a conflict on file arch/arm/mach-imx/clk-vf610.c.
parents 0df1f248 3db47dc0
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+23 −0
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i.mx6 Poweroff Driver

SNVS_LPCR in SNVS module can power off the whole system by pull
PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC.
If you don't want to use PMIC_ON_REQ as power on/off control,
please set status='disabled' to disable this driver.

Required Properties:
-compatible: "fsl,sec-v4.0-poweroff"
-reg: Specifies the physical address of the SNVS_LPCR register

Example:
	snvs@020cc000 {
		compatible = "fsl,sec-v4.0-mon", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x020cc000 0x4000>;
		.....
		snvs_poweroff: snvs-poweroff@38 {
			compatible = "fsl,sec-v4.0-poweroff";
			reg = <0x38 0x4>;
		};
	}
+1 −0
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@@ -97,6 +97,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_SPI_SPIDEV=y
CONFIG_GPIO_SYSFS=y
+1 −0
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@@ -158,6 +158,7 @@ CONFIG_I2C_CHARDEV=y
CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_IMX=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_MC9S08DZ60=y
+30 −1
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@@ -633,12 +633,41 @@ config SOC_VF610
	bool "Vybrid Family VF610 support"
	select ARM_GIC
	select PINCTRL_VF610
	select VF_PIT_TIMER
	select PL310_ERRATA_769419 if CACHE_L2X0

	help
	  This enable support for Freescale Vybrid VF610 processor.

choice
	prompt "Clocksource for scheduler clock"
	depends on SOC_VF610
	default VF_USE_ARM_GLOBAL_TIMER

	config VF_USE_ARM_GLOBAL_TIMER
		bool "Use ARM Global Timer"
		select ARM_GLOBAL_TIMER
		select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
		help
		  Use the ARM Global Timer as clocksource

	config VF_USE_PIT_TIMER
		bool "Use PIT timer"
		select VF_PIT_TIMER
		help
		  Use SoC Periodic Interrupt Timer (PIT) as clocksource

endchoice

config SOC_LS1021A
	bool "Freescale LS1021A support"
	select ARM_GIC
	select HAVE_ARM_ARCH_TIMER
	select PCI_DOMAINS if PCI
	select ZONE_DMA if ARM_LPAE

	help
	  This enable support for Freescale LS1021A processor.

endif

source "arch/arm/mach-imx/devices/Kconfig"
+4 −2
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@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o

imx5-pm-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o clk-cpu.o $(imx5-pm-y)

obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
			    clk-pfd.o clk-busy.o clk.o \
@@ -89,7 +89,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
ifdef CONFIG_SOC_IMX6
ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o

obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o

obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o

obj-y += devices/
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