Loading Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt +7 −0 Original line number Diff line number Diff line Loading @@ -147,6 +147,13 @@ First Level Node - CAM CPAS device Definition: Bool property specifying whether Clients are connected through CAMNOC for AXI access. - nvmem-cells Usage: optional Definition: nvmem cell node - nvmem-cell-names Usage: required Definition: If nvmem node is present, cell name is required =================================================================== Third Level Node - CAM AXI Port properties =================================================================== Loading arch/arm64/boot/dts/qcom/sdm670-camera.dtsi +6 −3 Original line number Diff line number Diff line Loading @@ -403,13 +403,16 @@ label = "cpas"; arch-compat = "cpas_top"; status = "ok"; reg-names = "cam_cpas_top", "cam_camnoc"; reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr"; reg = <0xac40000 0x1000>, <0xac42000 0x5000>; reg-cam-base = <0x40000 0x42000>; <0xac42000 0x5000>, <0x01fc0000 0x30000>; reg-cam-base = <0x40000 0x42000 0x0>; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; qcom,cpas-hw-ver = <0x170110>; /* Titan v170 v1.1.0 */ nvmem-cells = <&minor_rev>; nvmem-cell-names = "minor_rev"; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = "gcc_ahb_clk", Loading drivers/media/platform/msm/camera/cam_cpas/cam_cpas_soc.c +7 −0 Original line number Diff line number Diff line Loading @@ -140,6 +140,7 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, irq_handler_t irq_handler, void *irq_data) { int rc = 0; struct cam_cpas_private_soc *soc_private; rc = cam_soc_util_get_dt_properties(soc_info); if (rc) { Loading Loading @@ -173,6 +174,12 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, goto free_soc_private; } soc_private = soc_info->soc_private; soc_private->soc_id = cam_soc_util_get_soc_id(); soc_private->hw_rev = cam_soc_util_get_hw_revision_node(soc_info); CAM_DBG(CAM_CPAS, "soc id %d hw_rev %d", soc_private->soc_id, soc_private->hw_rev); return rc; free_soc_private: Loading drivers/media/platform/msm/camera/cam_cpas/cam_cpas_soc.h +4 −2 Original line number Diff line number Diff line Loading @@ -17,7 +17,6 @@ #include "cam_cpas_hw.h" #define CAM_REGULATOR_LEVEL_MAX 16 /** * struct cam_cpas_vdd_ahb_mapping : Voltage to ahb level mapping * Loading @@ -42,7 +41,8 @@ struct cam_cpas_vdd_ahb_mapping { * @axi_port_list_node : Node representing AXI Ports list * @num_vdd_ahb_mapping : Number of vdd to ahb level mapping supported * @vdd_ahb : AHB level mapping info for the supported vdd levels * * @soc_id : SOC id * @hw_rev : Camera hw revision */ struct cam_cpas_private_soc { const char *arch_compat; Loading @@ -54,6 +54,8 @@ struct cam_cpas_private_soc { struct device_node *axi_port_list_node; uint32_t num_vdd_ahb_mapping; struct cam_cpas_vdd_ahb_mapping vdd_ahb[CAM_REGULATOR_LEVEL_MAX]; uint32_t soc_id; uint32_t hw_rev; }; int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, Loading drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c +59 −0 Original line number Diff line number Diff line Loading @@ -114,6 +114,15 @@ static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info, return -EINVAL; } rc = cam_common_util_get_string_index(soc_info->mem_block_name, soc_info->num_mem_block, "core_top_csr_tcsr", &index); if ((rc == 0) && (index < num_reg_map)) { regbase_index[CAM_CPAS_REG_CSR_TCSR] = index; } else { CAM_DBG(CAM_CPAS, "regbase not found for CAMNOC, rc=%d, %d %d", rc, index, num_reg_map); } return 0; } Loading Loading @@ -456,6 +465,9 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data) static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) { int i; struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; struct cam_cpas_private_soc *soc_private = soc_info->soc_private; cam_cpastop_reset_irq(cpas_hw); Loading @@ -478,6 +490,29 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) } } if ((soc_private && soc_private->soc_id == SDM670_SOC_ID) && (soc_private->hw_rev == SDM670_V1_1)) { struct cam_cpas_reg *reg_info; int tcsr_index; void __iomem *mem_base; reg_info = &camnoc_info->errata_wa_list->tcsr_reg. tcsr_conn_box_spare_0; tcsr_index = cpas_core->regbase_index[CAM_CPAS_REG_CSR_TCSR]; if (tcsr_index == -1) { CAM_DBG(CAM_CPAS, "index in not initialized"); return 0; } mem_base = soc_info->reg_map[tcsr_index].mem_base; reg_info->value = TCSR_CONN_SET; cam_io_w_mb(reg_info->value, mem_base + reg_info->offset); CAM_DBG(CAM_CPAS, "tcsr(0x%lx) value %d", (unsigned long int)mem_base + reg_info->offset, cam_io_r_mb(mem_base + reg_info->offset)); } return 0; } Loading @@ -489,6 +524,8 @@ static int cam_cpastop_poweroff(struct cam_hw_info *cpas_hw) int rc = 0; struct cam_cpas_hw_errata_wa_list *errata_wa_list = camnoc_info->errata_wa_list; struct cam_cpas_private_soc *soc_private = cpas_hw->soc_info.soc_private; if (!errata_wa_list) return 0; Loading @@ -512,6 +549,28 @@ static int cam_cpastop_poweroff(struct cam_hw_info *cpas_hw) } } if ((soc_private && soc_private->soc_id == SDM670_SOC_ID) && (soc_private->hw_rev == SDM670_V1_1)) { struct cam_cpas_reg *reg_info; int tcsr_index; void __iomem *mem_base; reg_info = &camnoc_info->errata_wa_list->tcsr_reg. tcsr_conn_box_spare_0; reg_info->value = TCSR_CONN_RESET; tcsr_index = cpas_core->regbase_index[CAM_CPAS_REG_CSR_TCSR]; if (tcsr_index == -1) { CAM_DBG(CAM_CPAS, "index in not initialized"); return 0; } mem_base = soc_info->reg_map[tcsr_index].mem_base; cam_io_w_mb(reg_info->value, mem_base + reg_info->offset); CAM_DBG(CAM_CPAS, "tcsr(0x%lx) value %d", (unsigned long int)mem_base + reg_info->offset, cam_io_r_mb(mem_base + reg_info->offset)); } return rc; } Loading Loading
Documentation/devicetree/bindings/media/video/msm-cam-cpas.txt +7 −0 Original line number Diff line number Diff line Loading @@ -147,6 +147,13 @@ First Level Node - CAM CPAS device Definition: Bool property specifying whether Clients are connected through CAMNOC for AXI access. - nvmem-cells Usage: optional Definition: nvmem cell node - nvmem-cell-names Usage: required Definition: If nvmem node is present, cell name is required =================================================================== Third Level Node - CAM AXI Port properties =================================================================== Loading
arch/arm64/boot/dts/qcom/sdm670-camera.dtsi +6 −3 Original line number Diff line number Diff line Loading @@ -403,13 +403,16 @@ label = "cpas"; arch-compat = "cpas_top"; status = "ok"; reg-names = "cam_cpas_top", "cam_camnoc"; reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr"; reg = <0xac40000 0x1000>, <0xac42000 0x5000>; reg-cam-base = <0x40000 0x42000>; <0xac42000 0x5000>, <0x01fc0000 0x30000>; reg-cam-base = <0x40000 0x42000 0x0>; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; qcom,cpas-hw-ver = <0x170110>; /* Titan v170 v1.1.0 */ nvmem-cells = <&minor_rev>; nvmem-cell-names = "minor_rev"; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = "gcc_ahb_clk", Loading
drivers/media/platform/msm/camera/cam_cpas/cam_cpas_soc.c +7 −0 Original line number Diff line number Diff line Loading @@ -140,6 +140,7 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, irq_handler_t irq_handler, void *irq_data) { int rc = 0; struct cam_cpas_private_soc *soc_private; rc = cam_soc_util_get_dt_properties(soc_info); if (rc) { Loading Loading @@ -173,6 +174,12 @@ int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, goto free_soc_private; } soc_private = soc_info->soc_private; soc_private->soc_id = cam_soc_util_get_soc_id(); soc_private->hw_rev = cam_soc_util_get_hw_revision_node(soc_info); CAM_DBG(CAM_CPAS, "soc id %d hw_rev %d", soc_private->soc_id, soc_private->hw_rev); return rc; free_soc_private: Loading
drivers/media/platform/msm/camera/cam_cpas/cam_cpas_soc.h +4 −2 Original line number Diff line number Diff line Loading @@ -17,7 +17,6 @@ #include "cam_cpas_hw.h" #define CAM_REGULATOR_LEVEL_MAX 16 /** * struct cam_cpas_vdd_ahb_mapping : Voltage to ahb level mapping * Loading @@ -42,7 +41,8 @@ struct cam_cpas_vdd_ahb_mapping { * @axi_port_list_node : Node representing AXI Ports list * @num_vdd_ahb_mapping : Number of vdd to ahb level mapping supported * @vdd_ahb : AHB level mapping info for the supported vdd levels * * @soc_id : SOC id * @hw_rev : Camera hw revision */ struct cam_cpas_private_soc { const char *arch_compat; Loading @@ -54,6 +54,8 @@ struct cam_cpas_private_soc { struct device_node *axi_port_list_node; uint32_t num_vdd_ahb_mapping; struct cam_cpas_vdd_ahb_mapping vdd_ahb[CAM_REGULATOR_LEVEL_MAX]; uint32_t soc_id; uint32_t hw_rev; }; int cam_cpas_soc_init_resources(struct cam_hw_soc_info *soc_info, Loading
drivers/media/platform/msm/camera/cam_cpas/cpas_top/cam_cpastop_hw.c +59 −0 Original line number Diff line number Diff line Loading @@ -114,6 +114,15 @@ static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info, return -EINVAL; } rc = cam_common_util_get_string_index(soc_info->mem_block_name, soc_info->num_mem_block, "core_top_csr_tcsr", &index); if ((rc == 0) && (index < num_reg_map)) { regbase_index[CAM_CPAS_REG_CSR_TCSR] = index; } else { CAM_DBG(CAM_CPAS, "regbase not found for CAMNOC, rc=%d, %d %d", rc, index, num_reg_map); } return 0; } Loading Loading @@ -456,6 +465,9 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data) static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) { int i; struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; struct cam_cpas_private_soc *soc_private = soc_info->soc_private; cam_cpastop_reset_irq(cpas_hw); Loading @@ -478,6 +490,29 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) } } if ((soc_private && soc_private->soc_id == SDM670_SOC_ID) && (soc_private->hw_rev == SDM670_V1_1)) { struct cam_cpas_reg *reg_info; int tcsr_index; void __iomem *mem_base; reg_info = &camnoc_info->errata_wa_list->tcsr_reg. tcsr_conn_box_spare_0; tcsr_index = cpas_core->regbase_index[CAM_CPAS_REG_CSR_TCSR]; if (tcsr_index == -1) { CAM_DBG(CAM_CPAS, "index in not initialized"); return 0; } mem_base = soc_info->reg_map[tcsr_index].mem_base; reg_info->value = TCSR_CONN_SET; cam_io_w_mb(reg_info->value, mem_base + reg_info->offset); CAM_DBG(CAM_CPAS, "tcsr(0x%lx) value %d", (unsigned long int)mem_base + reg_info->offset, cam_io_r_mb(mem_base + reg_info->offset)); } return 0; } Loading @@ -489,6 +524,8 @@ static int cam_cpastop_poweroff(struct cam_hw_info *cpas_hw) int rc = 0; struct cam_cpas_hw_errata_wa_list *errata_wa_list = camnoc_info->errata_wa_list; struct cam_cpas_private_soc *soc_private = cpas_hw->soc_info.soc_private; if (!errata_wa_list) return 0; Loading @@ -512,6 +549,28 @@ static int cam_cpastop_poweroff(struct cam_hw_info *cpas_hw) } } if ((soc_private && soc_private->soc_id == SDM670_SOC_ID) && (soc_private->hw_rev == SDM670_V1_1)) { struct cam_cpas_reg *reg_info; int tcsr_index; void __iomem *mem_base; reg_info = &camnoc_info->errata_wa_list->tcsr_reg. tcsr_conn_box_spare_0; reg_info->value = TCSR_CONN_RESET; tcsr_index = cpas_core->regbase_index[CAM_CPAS_REG_CSR_TCSR]; if (tcsr_index == -1) { CAM_DBG(CAM_CPAS, "index in not initialized"); return 0; } mem_base = soc_info->reg_map[tcsr_index].mem_base; cam_io_w_mb(reg_info->value, mem_base + reg_info->offset); CAM_DBG(CAM_CPAS, "tcsr(0x%lx) value %d", (unsigned long int)mem_base + reg_info->offset, cam_io_r_mb(mem_base + reg_info->offset)); } return rc; } Loading