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Commit 2cd94b13 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

ARM: dts: msm: remove clk_src entries from sdm845 target 



Clock enable and disable are no_op for core and vsync
clk source. Remove these two clock entries from sdm845
target for sde hardware.

Change-Id: Ia156387b1b3e6dc3a476f43b472f29780a88b8b4
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 446446e7

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+4 −7
Original line number Diff line number Diff line
@@ -23,15 +23,12 @@ 
			<&clock_gcc GCC_DISP_AXI_CLK>,

			<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,

			<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK_SRC>,

			<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,

			<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;

		clock-names = "gcc_iface", "gcc_bus",

			"iface_clk", "bus_clk", "core_clk_src",

			"vsync_clk_src", "core_clk", "vsync_clk";

		clock-rate = <0 0 0 0 300000000 0 300000000 0 0>;

		clock-max-rate = <0 0 0 0 430000000 0 430000000 0 0>;

		clock-names = "gcc_iface", "gcc_bus", "iface_clk",

				"bus_clk", "core_clk", "vsync_clk";

		clock-rate = <0 0 0 0 300000000 19200000 0>;

		clock-max-rate = <0 0 0 0 430000000 19200000 0>;



		sde-vdd-supply = <&mdss_core_gdsc>;