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Commit 2ccd71f1 authored by Borislav Petkov's avatar Borislav Petkov Committed by Thomas Gleixner
Browse files

x86/cpufeature: Move some of the scattered feature bits to x86_capability 



Turn the CPUID leafs which are proper CPUID feature bit leafs into
separate ->x86_capability words.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1449481182-27541-2-git-send-email-bp@alien8.de


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 0fa85119

arch/x86/include/asm/cpufeature.h

+32 −22
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <asm/disabled-features.h>

#endif



#define NCAPINTS	14	/* N 32-bit words worth of info */

#define NCAPINTS	16	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */



/*
@@ -181,22 +181,17 @@ 


/*

 * Auxiliary flags: Linux defined - For features scattered in various

 * CPUID levels like 0x6, 0xA etc, word 7

 * CPUID levels like 0x6, 0xA etc, word 7.

 *

 * Reuse free bits when adding new feature flags!

 */

#define X86_FEATURE_IDA		( 7*32+ 0) /* Intel Dynamic Acceleration */

#define X86_FEATURE_ARAT	( 7*32+ 1) /* Always Running APIC Timer */



#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_PLN		( 7*32+ 5) /* Intel Power Limit Notification */

#define X86_FEATURE_PTS		( 7*32+ 6) /* Intel Package Thermal Status */

#define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */



#define X86_FEATURE_HW_PSTATE	( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_HWP		( 7*32+ 10) /* "hwp" Intel HWP */

#define X86_FEATURE_HWP_NOTIFY	( 7*32+ 11) /* Intel HWP_NOTIFY */

#define X86_FEATURE_HWP_ACT_WINDOW ( 7*32+ 12) /* Intel HWP_ACT_WINDOW */

#define X86_FEATURE_HWP_EPP	( 7*32+13) /* Intel HWP_EPP */

#define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */



#define X86_FEATURE_INTEL_PT	( 7*32+15) /* Intel Processor Trace */



/* Virtualization flags: Linux defined, word 8 */
@@ -205,16 +200,7 @@ 
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */

#define X86_FEATURE_EPT         ( 8*32+ 3) /* Intel Extended Page Table */

#define X86_FEATURE_VPID        ( 8*32+ 4) /* Intel Virtual Processor ID */

#define X86_FEATURE_NPT		( 8*32+ 5) /* AMD Nested Page Table support */

#define X86_FEATURE_LBRV	( 8*32+ 6) /* AMD LBR Virtualization support */

#define X86_FEATURE_SVML	( 8*32+ 7) /* "svm_lock" AMD SVM locking MSR */

#define X86_FEATURE_NRIPS	( 8*32+ 8) /* "nrip_save" AMD SVM next_rip save */

#define X86_FEATURE_TSCRATEMSR  ( 8*32+ 9) /* "tsc_scale" AMD TSC scaling support */

#define X86_FEATURE_VMCBCLEAN   ( 8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */

#define X86_FEATURE_FLUSHBYASID ( 8*32+11) /* AMD flush-by-ASID support */

#define X86_FEATURE_DECODEASSISTS ( 8*32+12) /* AMD Decode Assists support */

#define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */

#define X86_FEATURE_PFTHRESHOLD ( 8*32+14) /* AMD pause filter threshold */



#define X86_FEATURE_VMMCALL     ( 8*32+15) /* Prefer vmmcall to vmcall */
@@ -258,6 +244,30 @@ 
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */

#define X86_FEATURE_CLZERO	(13*32+0) /* CLZERO instruction */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */

#define X86_FEATURE_DTHERM	(14*32+ 0) /* Digital Thermal Sensor */

#define X86_FEATURE_IDA		(14*32+ 1) /* Intel Dynamic Acceleration */

#define X86_FEATURE_ARAT	(14*32+ 2) /* Always Running APIC Timer */

#define X86_FEATURE_PLN		(14*32+ 4) /* Intel Power Limit Notification */

#define X86_FEATURE_PTS		(14*32+ 6) /* Intel Package Thermal Status */

#define X86_FEATURE_HWP		(14*32+ 7) /* Intel Hardware P-states */

#define X86_FEATURE_HWP_NOTIFY	(14*32+ 8) /* HWP Notification */

#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */

#define X86_FEATURE_HWP_EPP	(14*32+10) /* HWP Energy Perf. Preference */

#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */



/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */

#define X86_FEATURE_NPT		(15*32+ 0) /* Nested Page Table support */

#define X86_FEATURE_LBRV	(15*32+ 1) /* LBR Virtualization support */

#define X86_FEATURE_SVML	(15*32+ 2) /* "svm_lock" SVM locking MSR */

#define X86_FEATURE_NRIPS	(15*32+ 3) /* "nrip_save" SVM next_rip save */

#define X86_FEATURE_TSCRATEMSR  (15*32+ 4) /* "tsc_scale" TSC scaling support */

#define X86_FEATURE_VMCBCLEAN   (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */

#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */

#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */

#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */

#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */



/*

 * BUG word(s)

 */

arch/x86/kernel/cpu/common.c

+5 −0
Original line number Diff line number Diff line
@@ -618,6 +618,8 @@ void get_cpu_cap(struct cpuinfo_x86 *c) 
		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);



		c->x86_capability[9] = ebx;



		c->x86_capability[14] = cpuid_eax(0x00000006);

	}



	/* Extended state features: level 0x0000000d */
@@ -679,6 +681,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) 
	if (c->extended_cpuid_level >= 0x80000007)

		c->x86_power = cpuid_edx(0x80000007);



	if (c->extended_cpuid_level >= 0x8000000a)

		c->x86_capability[15] = cpuid_edx(0x8000000a);



	init_scattered_cpuid_features(c);

}

arch/x86/kernel/cpu/scattered.c

+0 −20
Original line number Diff line number Diff line
@@ -31,32 +31,12 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c) 
	const struct cpuid_bit *cb;



	static const struct cpuid_bit cpuid_bits[] = {

		{ X86_FEATURE_DTHERM,		CR_EAX, 0, 0x00000006, 0 },

		{ X86_FEATURE_IDA,		CR_EAX, 1, 0x00000006, 0 },

		{ X86_FEATURE_ARAT,		CR_EAX, 2, 0x00000006, 0 },

		{ X86_FEATURE_PLN,		CR_EAX, 4, 0x00000006, 0 },

		{ X86_FEATURE_PTS,		CR_EAX, 6, 0x00000006, 0 },

		{ X86_FEATURE_HWP,		CR_EAX, 7, 0x00000006, 0 },

		{ X86_FEATURE_HWP_NOTIFY,	CR_EAX, 8, 0x00000006, 0 },

		{ X86_FEATURE_HWP_ACT_WINDOW,	CR_EAX, 9, 0x00000006, 0 },

		{ X86_FEATURE_HWP_EPP,		CR_EAX,10, 0x00000006, 0 },

		{ X86_FEATURE_HWP_PKG_REQ,	CR_EAX,11, 0x00000006, 0 },

		{ X86_FEATURE_INTEL_PT,		CR_EBX,25, 0x00000007, 0 },

		{ X86_FEATURE_APERFMPERF,	CR_ECX, 0, 0x00000006, 0 },

		{ X86_FEATURE_EPB,		CR_ECX, 3, 0x00000006, 0 },

		{ X86_FEATURE_HW_PSTATE,	CR_EDX, 7, 0x80000007, 0 },

		{ X86_FEATURE_CPB,		CR_EDX, 9, 0x80000007, 0 },

		{ X86_FEATURE_PROC_FEEDBACK,	CR_EDX,11, 0x80000007, 0 },

		{ X86_FEATURE_NPT,		CR_EDX, 0, 0x8000000a, 0 },

		{ X86_FEATURE_LBRV,		CR_EDX, 1, 0x8000000a, 0 },

		{ X86_FEATURE_SVML,		CR_EDX, 2, 0x8000000a, 0 },

		{ X86_FEATURE_NRIPS,		CR_EDX, 3, 0x8000000a, 0 },

		{ X86_FEATURE_TSCRATEMSR,	CR_EDX, 4, 0x8000000a, 0 },

		{ X86_FEATURE_VMCBCLEAN,	CR_EDX, 5, 0x8000000a, 0 },

		{ X86_FEATURE_FLUSHBYASID,	CR_EDX, 6, 0x8000000a, 0 },

		{ X86_FEATURE_DECODEASSISTS,	CR_EDX, 7, 0x8000000a, 0 },

		{ X86_FEATURE_PAUSEFILTER,	CR_EDX,10, 0x8000000a, 0 },

		{ X86_FEATURE_PFTHRESHOLD,	CR_EDX,12, 0x8000000a, 0 },

		{ 0, 0, 0, 0, 0 }

	};