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Commit 2bfd8c8a authored by mohamed sunfeer's avatar mohamed sunfeer Committed by Brahmaji K
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ARM: dts: msm: Enable QSEECOM driver for SDM450 



Enable qseecom driver node on Device tree include file to
enable the qseecom driver to communicate with TZ.

Change-Id: I3b9d35f6cf31b264e49174a8b1881a3d3ac9fce7
Signed-off-by: default avatarmohamed sunfeer <msunfeer@codeaurora.org>
Signed-off-by: default avatarBrahmaji K <bkomma@codeaurora.org>
parent 7662b4eb

arch/arm64/boot/dts/qcom/msm8953.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -482,6 +482,34 @@ 
		#thermal-sensor-cells = <1>;

	};



	qcom_seecom: qseecom@85b00000 {

		compatible = "qcom,qseecom";

		reg = <0x85b00000 0x800000>;

		reg-names = "secapp-region";

		qcom,hlos-num-ce-hw-instances = <1>;

		qcom,hlos-ce-hw-instance = <0>;

		qcom,qsee-ce-hw-instance = <0>;

		qcom,disk-encrypt-pipe-pair = <2>;

		qcom,support-fde;

		qcom,msm-bus,name = "qseecom-noc";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,support-bus-scaling;

		qcom,msm-bus,vectors-KBps =

			<55 512 0 0>,

			<55 512 0 0>,

			<55 512 120000 1200000>,

			<55 512 393600 3936000>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

		status = "disabled";

	};



	blsp1_uart0: serial@78af000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0x78af000 0x200>;