OMAP3 PRCM: convert OMAP3 PRCM macros to the _SHIFT/_MASK suffixes (2bc4ef71) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/mach-omap2/cm-regbits-34xx.h

+111 −111

Original line number	Original line	Diff line number	Diff line
	@@ -21,15 +21,15 @@
	/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */		/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
	#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)		#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
	#define OMAP3430ES2_EN_MMC3_SHIFT 30		#define OMAP3430ES2_EN_MMC3_SHIFT 30
	#define OMAP3430_EN_MSPRO (1 << 23)		#define OMAP3430_EN_MSPRO_MASK (1 << 23)
	#define OMAP3430_EN_MSPRO_SHIFT 23		#define OMAP3430_EN_MSPRO_SHIFT 23
	#define OMAP3430_EN_HDQ (1 << 22)		#define OMAP3430_EN_HDQ_MASK (1 << 22)
	#define OMAP3430_EN_HDQ_SHIFT 22		#define OMAP3430_EN_HDQ_SHIFT 22
	#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)		#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
	#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5		#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
	#define OMAP3430ES1_EN_D2D (1 << 3)		#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
	#define OMAP3430ES1_EN_D2D_SHIFT 3		#define OMAP3430ES1_EN_D2D_SHIFT 3
	#define OMAP3430_EN_SSI (1 << 0)		#define OMAP3430_EN_SSI_MASK (1 << 0)
	#define OMAP3430_EN_SSI_SHIFT 0		#define OMAP3430_EN_SSI_SHIFT 0

	/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */		/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
	@@ -37,19 +37,19 @@
	#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)		#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)

	/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */		/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
	#define OMAP3430_EN_WDT2 (1 << 5)		#define OMAP3430_EN_WDT2_MASK (1 << 5)
	#define OMAP3430_EN_WDT2_SHIFT 5		#define OMAP3430_EN_WDT2_SHIFT 5

	/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */		/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
	#define OMAP3430_EN_CAM (1 << 0)		#define OMAP3430_EN_CAM_MASK (1 << 0)
	#define OMAP3430_EN_CAM_SHIFT 0		#define OMAP3430_EN_CAM_SHIFT 0

	/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */		/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
	#define OMAP3430_EN_WDT3 (1 << 12)		#define OMAP3430_EN_WDT3_MASK (1 << 12)
	#define OMAP3430_EN_WDT3_SHIFT 12		#define OMAP3430_EN_WDT3_SHIFT 12

	/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */		/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
	#define OMAP3430_OVERRIDE_ENABLE (1 << 19)		#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)


	/* Bits specific to each register */		/* Bits specific to each register */
	@@ -69,7 +69,7 @@
	#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)		#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)

	/* CM_IDLEST_IVA2 */		/* CM_IDLEST_IVA2 */
	#define OMAP3430_ST_IVA2 (1 << 0)		#define OMAP3430_ST_IVA2_MASK (1 << 0)

	/* CM_IDLEST_PLL_IVA2 */		/* CM_IDLEST_PLL_IVA2 */
	#define OMAP3430_ST_IVA2_CLK_SHIFT 0		#define OMAP3430_ST_IVA2_CLK_SHIFT 0
	@@ -114,7 +114,7 @@
	#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)		#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)

	/* CM_IDLEST_MPU */		/* CM_IDLEST_MPU */
	#define OMAP3430_ST_MPU (1 << 0)		#define OMAP3430_ST_MPU_MASK (1 << 0)

	/* CM_IDLEST_PLL_MPU */		/* CM_IDLEST_PLL_MPU */
	#define OMAP3430_ST_MPU_CLK_SHIFT 0		#define OMAP3430_ST_MPU_CLK_SHIFT 0
	@@ -145,27 +145,27 @@
	#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)		#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)

	/* CM_FCLKEN1_CORE specific bits */		/* CM_FCLKEN1_CORE specific bits */
	#define OMAP3430_EN_MODEM (1 << 31)		#define OMAP3430_EN_MODEM_MASK (1 << 31)
	#define OMAP3430_EN_MODEM_SHIFT 31		#define OMAP3430_EN_MODEM_SHIFT 31

	/* CM_ICLKEN1_CORE specific bits */		/* CM_ICLKEN1_CORE specific bits */
	#define OMAP3430_EN_ICR (1 << 29)		#define OMAP3430_EN_ICR_MASK (1 << 29)
	#define OMAP3430_EN_ICR_SHIFT 29		#define OMAP3430_EN_ICR_SHIFT 29
	#define OMAP3430_EN_AES2 (1 << 28)		#define OMAP3430_EN_AES2_MASK (1 << 28)
	#define OMAP3430_EN_AES2_SHIFT 28		#define OMAP3430_EN_AES2_SHIFT 28
	#define OMAP3430_EN_SHA12 (1 << 27)		#define OMAP3430_EN_SHA12_MASK (1 << 27)
	#define OMAP3430_EN_SHA12_SHIFT 27		#define OMAP3430_EN_SHA12_SHIFT 27
	#define OMAP3430_EN_DES2 (1 << 26)		#define OMAP3430_EN_DES2_MASK (1 << 26)
	#define OMAP3430_EN_DES2_SHIFT 26		#define OMAP3430_EN_DES2_SHIFT 26
	#define OMAP3430ES1_EN_FAC (1 << 8)		#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
	#define OMAP3430ES1_EN_FAC_SHIFT 8		#define OMAP3430ES1_EN_FAC_SHIFT 8
	#define OMAP3430_EN_MAILBOXES (1 << 7)		#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
	#define OMAP3430_EN_MAILBOXES_SHIFT 7		#define OMAP3430_EN_MAILBOXES_SHIFT 7
	#define OMAP3430_EN_OMAPCTRL (1 << 6)		#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
	#define OMAP3430_EN_OMAPCTRL_SHIFT 6		#define OMAP3430_EN_OMAPCTRL_SHIFT 6
	#define OMAP3430_EN_SAD2D (1 << 3)		#define OMAP3430_EN_SAD2D_MASK (1 << 3)
	#define OMAP3430_EN_SAD2D_SHIFT 3		#define OMAP3430_EN_SAD2D_SHIFT 3
	#define OMAP3430_EN_SDRC (1 << 1)		#define OMAP3430_EN_SDRC_MASK (1 << 1)
	#define OMAP3430_EN_SDRC_SHIFT 1		#define OMAP3430_EN_SDRC_SHIFT 1

	/* AM35XX specific CM_ICLKEN1_CORE bits */		/* AM35XX specific CM_ICLKEN1_CORE bits */
	@@ -175,20 +175,20 @@
	#define AM35XX_EN_UART4_SHIFT 23		#define AM35XX_EN_UART4_SHIFT 23

	/* CM_ICLKEN2_CORE */		/* CM_ICLKEN2_CORE */
	#define OMAP3430_EN_PKA (1 << 4)		#define OMAP3430_EN_PKA_MASK (1 << 4)
	#define OMAP3430_EN_PKA_SHIFT 4		#define OMAP3430_EN_PKA_SHIFT 4
	#define OMAP3430_EN_AES1 (1 << 3)		#define OMAP3430_EN_AES1_MASK (1 << 3)
	#define OMAP3430_EN_AES1_SHIFT 3		#define OMAP3430_EN_AES1_SHIFT 3
	#define OMAP3430_EN_RNG (1 << 2)		#define OMAP3430_EN_RNG_MASK (1 << 2)
	#define OMAP3430_EN_RNG_SHIFT 2		#define OMAP3430_EN_RNG_SHIFT 2
	#define OMAP3430_EN_SHA11 (1 << 1)		#define OMAP3430_EN_SHA11_MASK (1 << 1)
	#define OMAP3430_EN_SHA11_SHIFT 1		#define OMAP3430_EN_SHA11_SHIFT 1
	#define OMAP3430_EN_DES1 (1 << 0)		#define OMAP3430_EN_DES1_MASK (1 << 0)
	#define OMAP3430_EN_DES1_SHIFT 0		#define OMAP3430_EN_DES1_SHIFT 0

	/* CM_ICLKEN3_CORE */		/* CM_ICLKEN3_CORE */
	#define OMAP3430_EN_MAD2D_SHIFT 3		#define OMAP3430_EN_MAD2D_SHIFT 3
	#define OMAP3430_EN_MAD2D (1 << 3)		#define OMAP3430_EN_MAD2D_MASK (1 << 3)

	/* CM_FCLKEN3_CORE specific bits */		/* CM_FCLKEN3_CORE specific bits */
	#define OMAP3430ES2_EN_TS_SHIFT 1		#define OMAP3430ES2_EN_TS_SHIFT 1
	@@ -249,79 +249,79 @@
	#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)		#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)

	/* CM_AUTOIDLE1_CORE */		/* CM_AUTOIDLE1_CORE */
	#define OMAP3430_AUTO_MODEM (1 << 31)		#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
	#define OMAP3430_AUTO_MODEM_SHIFT 31		#define OMAP3430_AUTO_MODEM_SHIFT 31
	#define OMAP3430ES2_AUTO_MMC3 (1 << 30)		#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
	#define OMAP3430ES2_AUTO_MMC3_SHIFT 30		#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
	#define OMAP3430ES2_AUTO_ICR (1 << 29)		#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
	#define OMAP3430ES2_AUTO_ICR_SHIFT 29		#define OMAP3430ES2_AUTO_ICR_SHIFT 29
	#define OMAP3430_AUTO_AES2 (1 << 28)		#define OMAP3430_AUTO_AES2_MASK (1 << 28)
	#define OMAP3430_AUTO_AES2_SHIFT 28		#define OMAP3430_AUTO_AES2_SHIFT 28
	#define OMAP3430_AUTO_SHA12 (1 << 27)		#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
	#define OMAP3430_AUTO_SHA12_SHIFT 27		#define OMAP3430_AUTO_SHA12_SHIFT 27
	#define OMAP3430_AUTO_DES2 (1 << 26)		#define OMAP3430_AUTO_DES2_MASK (1 << 26)
	#define OMAP3430_AUTO_DES2_SHIFT 26		#define OMAP3430_AUTO_DES2_SHIFT 26
	#define OMAP3430_AUTO_MMC2 (1 << 25)		#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
	#define OMAP3430_AUTO_MMC2_SHIFT 25		#define OMAP3430_AUTO_MMC2_SHIFT 25
	#define OMAP3430_AUTO_MMC1 (1 << 24)		#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
	#define OMAP3430_AUTO_MMC1_SHIFT 24		#define OMAP3430_AUTO_MMC1_SHIFT 24
	#define OMAP3430_AUTO_MSPRO (1 << 23)		#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
	#define OMAP3430_AUTO_MSPRO_SHIFT 23		#define OMAP3430_AUTO_MSPRO_SHIFT 23
	#define OMAP3430_AUTO_HDQ (1 << 22)		#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
	#define OMAP3430_AUTO_HDQ_SHIFT 22		#define OMAP3430_AUTO_HDQ_SHIFT 22
	#define OMAP3430_AUTO_MCSPI4 (1 << 21)		#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
	#define OMAP3430_AUTO_MCSPI4_SHIFT 21		#define OMAP3430_AUTO_MCSPI4_SHIFT 21
	#define OMAP3430_AUTO_MCSPI3 (1 << 20)		#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
	#define OMAP3430_AUTO_MCSPI3_SHIFT 20		#define OMAP3430_AUTO_MCSPI3_SHIFT 20
	#define OMAP3430_AUTO_MCSPI2 (1 << 19)		#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
	#define OMAP3430_AUTO_MCSPI2_SHIFT 19		#define OMAP3430_AUTO_MCSPI2_SHIFT 19
	#define OMAP3430_AUTO_MCSPI1 (1 << 18)		#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
	#define OMAP3430_AUTO_MCSPI1_SHIFT 18		#define OMAP3430_AUTO_MCSPI1_SHIFT 18
	#define OMAP3430_AUTO_I2C3 (1 << 17)		#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
	#define OMAP3430_AUTO_I2C3_SHIFT 17		#define OMAP3430_AUTO_I2C3_SHIFT 17
	#define OMAP3430_AUTO_I2C2 (1 << 16)		#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
	#define OMAP3430_AUTO_I2C2_SHIFT 16		#define OMAP3430_AUTO_I2C2_SHIFT 16
	#define OMAP3430_AUTO_I2C1 (1 << 15)		#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
	#define OMAP3430_AUTO_I2C1_SHIFT 15		#define OMAP3430_AUTO_I2C1_SHIFT 15
	#define OMAP3430_AUTO_UART2 (1 << 14)		#define OMAP3430_AUTO_UART2_MASK (1 << 14)
	#define OMAP3430_AUTO_UART2_SHIFT 14		#define OMAP3430_AUTO_UART2_SHIFT 14
	#define OMAP3430_AUTO_UART1 (1 << 13)		#define OMAP3430_AUTO_UART1_MASK (1 << 13)
	#define OMAP3430_AUTO_UART1_SHIFT 13		#define OMAP3430_AUTO_UART1_SHIFT 13
	#define OMAP3430_AUTO_GPT11 (1 << 12)		#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
	#define OMAP3430_AUTO_GPT11_SHIFT 12		#define OMAP3430_AUTO_GPT11_SHIFT 12
	#define OMAP3430_AUTO_GPT10 (1 << 11)		#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
	#define OMAP3430_AUTO_GPT10_SHIFT 11		#define OMAP3430_AUTO_GPT10_SHIFT 11
	#define OMAP3430_AUTO_MCBSP5 (1 << 10)		#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
	#define OMAP3430_AUTO_MCBSP5_SHIFT 10		#define OMAP3430_AUTO_MCBSP5_SHIFT 10
	#define OMAP3430_AUTO_MCBSP1 (1 << 9)		#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
	#define OMAP3430_AUTO_MCBSP1_SHIFT 9		#define OMAP3430_AUTO_MCBSP1_SHIFT 9
	#define OMAP3430ES1_AUTO_FAC (1 << 8)		#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
	#define OMAP3430ES1_AUTO_FAC_SHIFT 8		#define OMAP3430ES1_AUTO_FAC_SHIFT 8
	#define OMAP3430_AUTO_MAILBOXES (1 << 7)		#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
	#define OMAP3430_AUTO_MAILBOXES_SHIFT 7		#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
	#define OMAP3430_AUTO_OMAPCTRL (1 << 6)		#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
	#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6		#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
	#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)		#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
	#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5		#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
	#define OMAP3430_AUTO_HSOTGUSB (1 << 4)		#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
	#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4		#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
	#define OMAP3430ES1_AUTO_D2D (1 << 3)		#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
	#define OMAP3430ES1_AUTO_D2D_SHIFT 3		#define OMAP3430ES1_AUTO_D2D_SHIFT 3
	#define OMAP3430_AUTO_SAD2D (1 << 3)		#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
	#define OMAP3430_AUTO_SAD2D_SHIFT 3		#define OMAP3430_AUTO_SAD2D_SHIFT 3
	#define OMAP3430_AUTO_SSI (1 << 0)		#define OMAP3430_AUTO_SSI_MASK (1 << 0)
	#define OMAP3430_AUTO_SSI_SHIFT 0		#define OMAP3430_AUTO_SSI_SHIFT 0

	/* CM_AUTOIDLE2_CORE */		/* CM_AUTOIDLE2_CORE */
	#define OMAP3430_AUTO_PKA (1 << 4)		#define OMAP3430_AUTO_PKA_MASK (1 << 4)
	#define OMAP3430_AUTO_PKA_SHIFT 4		#define OMAP3430_AUTO_PKA_SHIFT 4
	#define OMAP3430_AUTO_AES1 (1 << 3)		#define OMAP3430_AUTO_AES1_MASK (1 << 3)
	#define OMAP3430_AUTO_AES1_SHIFT 3		#define OMAP3430_AUTO_AES1_SHIFT 3
	#define OMAP3430_AUTO_RNG (1 << 2)		#define OMAP3430_AUTO_RNG_MASK (1 << 2)
	#define OMAP3430_AUTO_RNG_SHIFT 2		#define OMAP3430_AUTO_RNG_SHIFT 2
	#define OMAP3430_AUTO_SHA11 (1 << 1)		#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
	#define OMAP3430_AUTO_SHA11_SHIFT 1		#define OMAP3430_AUTO_SHA11_SHIFT 1
	#define OMAP3430_AUTO_DES1 (1 << 0)		#define OMAP3430_AUTO_DES1_MASK (1 << 0)
	#define OMAP3430_AUTO_DES1_SHIFT 0		#define OMAP3430_AUTO_DES1_SHIFT 0

	/* CM_AUTOIDLE3_CORE */		/* CM_AUTOIDLE3_CORE */
	@@ -331,7 +331,7 @@
	#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2		#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
	#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)		#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
	#define OMAP3430_AUTO_MAD2D_SHIFT 3		#define OMAP3430_AUTO_MAD2D_SHIFT 3
	#define OMAP3430_AUTO_MAD2D (1 << 3)		#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)

	/* CM_CLKSEL_CORE */		/* CM_CLKSEL_CORE */
	#define OMAP3430_CLKSEL_SSI_SHIFT 8		#define OMAP3430_CLKSEL_SSI_SHIFT 8
	@@ -366,9 +366,9 @@
	#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)		#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)

	/* CM_FCLKEN_GFX */		/* CM_FCLKEN_GFX */
	#define OMAP3430ES1_EN_3D (1 << 2)		#define OMAP3430ES1_EN_3D_MASK (1 << 2)
	#define OMAP3430ES1_EN_3D_SHIFT 2		#define OMAP3430ES1_EN_3D_SHIFT 2
	#define OMAP3430ES1_EN_2D (1 << 1)		#define OMAP3430ES1_EN_2D_MASK (1 << 1)
	#define OMAP3430ES1_EN_2D_SHIFT 1		#define OMAP3430ES1_EN_2D_SHIFT 1

	/* CM_ICLKEN_GFX specific bits */		/* CM_ICLKEN_GFX specific bits */
	@@ -416,9 +416,9 @@
	#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)		#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)

	/* CM_ICLKEN_WKUP specific bits */		/* CM_ICLKEN_WKUP specific bits */
	#define OMAP3430_EN_WDT1 (1 << 4)		#define OMAP3430_EN_WDT1_MASK (1 << 4)
	#define OMAP3430_EN_WDT1_SHIFT 4		#define OMAP3430_EN_WDT1_SHIFT 4
	#define OMAP3430_EN_32KSYNC (1 << 2)		#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
	#define OMAP3430_EN_32KSYNC_SHIFT 2		#define OMAP3430_EN_32KSYNC_SHIFT 2

	/* CM_IDLEST_WKUP specific bits */		/* CM_IDLEST_WKUP specific bits */
	@@ -432,19 +432,19 @@
	#define OMAP3430_ST_32KSYNC_MASK (1 << 2)		#define OMAP3430_ST_32KSYNC_MASK (1 << 2)

	/* CM_AUTOIDLE_WKUP */		/* CM_AUTOIDLE_WKUP */
	#define OMAP3430ES2_AUTO_USIMOCP (1 << 9)		#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
	#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9		#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
	#define OMAP3430_AUTO_WDT2 (1 << 5)		#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
	#define OMAP3430_AUTO_WDT2_SHIFT 5		#define OMAP3430_AUTO_WDT2_SHIFT 5
	#define OMAP3430_AUTO_WDT1 (1 << 4)		#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
	#define OMAP3430_AUTO_WDT1_SHIFT 4		#define OMAP3430_AUTO_WDT1_SHIFT 4
	#define OMAP3430_AUTO_GPIO1 (1 << 3)		#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
	#define OMAP3430_AUTO_GPIO1_SHIFT 3		#define OMAP3430_AUTO_GPIO1_SHIFT 3
	#define OMAP3430_AUTO_32KSYNC (1 << 2)		#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
	#define OMAP3430_AUTO_32KSYNC_SHIFT 2		#define OMAP3430_AUTO_32KSYNC_SHIFT 2
	#define OMAP3430_AUTO_GPT12 (1 << 1)		#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
	#define OMAP3430_AUTO_GPT12_SHIFT 1		#define OMAP3430_AUTO_GPT12_SHIFT 1
	#define OMAP3430_AUTO_GPT1 (1 << 0)		#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
	#define OMAP3430_AUTO_GPT1_SHIFT 0		#define OMAP3430_AUTO_GPT1_SHIFT 0

	/* CM_CLKSEL_WKUP */		/* CM_CLKSEL_WKUP */
	@@ -488,10 +488,10 @@
	#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)		#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)

	/* CM_IDLEST_CKGEN */		/* CM_IDLEST_CKGEN */
	#define OMAP3430_ST_54M_CLK (1 << 5)		#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
	#define OMAP3430_ST_12M_CLK (1 << 4)		#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
	#define OMAP3430_ST_48M_CLK (1 << 3)		#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
	#define OMAP3430_ST_96M_CLK (1 << 2)		#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
	#define OMAP3430_ST_PERIPH_CLK_SHIFT 1		#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
	#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)		#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
	#define OMAP3430_ST_CORE_CLK_SHIFT 0		#define OMAP3430_ST_CORE_CLK_SHIFT 0
	@@ -558,22 +558,22 @@

	/* CM_CLKOUT_CTRL */		/* CM_CLKOUT_CTRL */
	#define OMAP3430_CLKOUT2_EN_SHIFT 7		#define OMAP3430_CLKOUT2_EN_SHIFT 7
	#define OMAP3430_CLKOUT2_EN (1 << 7)		#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
	#define OMAP3430_CLKOUT2_DIV_SHIFT 3		#define OMAP3430_CLKOUT2_DIV_SHIFT 3
	#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)		#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
	#define OMAP3430_CLKOUT2SOURCE_SHIFT 0		#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
	#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)		#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)

	/* CM_FCLKEN_DSS */		/* CM_FCLKEN_DSS */
	#define OMAP3430_EN_TV (1 << 2)		#define OMAP3430_EN_TV_MASK (1 << 2)
	#define OMAP3430_EN_TV_SHIFT 2		#define OMAP3430_EN_TV_SHIFT 2
	#define OMAP3430_EN_DSS2 (1 << 1)		#define OMAP3430_EN_DSS2_MASK (1 << 1)
	#define OMAP3430_EN_DSS2_SHIFT 1		#define OMAP3430_EN_DSS2_SHIFT 1
	#define OMAP3430_EN_DSS1 (1 << 0)		#define OMAP3430_EN_DSS1_MASK (1 << 0)
	#define OMAP3430_EN_DSS1_SHIFT 0		#define OMAP3430_EN_DSS1_SHIFT 0

	/* CM_ICLKEN_DSS */		/* CM_ICLKEN_DSS */
	#define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)		#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
	#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0		#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0

	/* CM_IDLEST_DSS */		/* CM_IDLEST_DSS */
	@@ -585,7 +585,7 @@
	#define OMAP3430ES1_ST_DSS_MASK (1 << 0)		#define OMAP3430ES1_ST_DSS_MASK (1 << 0)

	/* CM_AUTOIDLE_DSS */		/* CM_AUTOIDLE_DSS */
	#define OMAP3430_AUTO_DSS (1 << 0)		#define OMAP3430_AUTO_DSS_MASK (1 << 0)
	#define OMAP3430_AUTO_DSS_SHIFT 0		#define OMAP3430_AUTO_DSS_SHIFT 0

	/* CM_CLKSEL_DSS */		/* CM_CLKSEL_DSS */
	@@ -607,16 +607,16 @@
	#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)		#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)

	/* CM_FCLKEN_CAM specific bits */		/* CM_FCLKEN_CAM specific bits */
	#define OMAP3430_EN_CSI2 (1 << 1)		#define OMAP3430_EN_CSI2_MASK (1 << 1)
	#define OMAP3430_EN_CSI2_SHIFT 1		#define OMAP3430_EN_CSI2_SHIFT 1

	/* CM_ICLKEN_CAM specific bits */		/* CM_ICLKEN_CAM specific bits */

	/* CM_IDLEST_CAM */		/* CM_IDLEST_CAM */
	#define OMAP3430_ST_CAM (1 << 0)		#define OMAP3430_ST_CAM_MASK (1 << 0)

	/* CM_AUTOIDLE_CAM */		/* CM_AUTOIDLE_CAM */
	#define OMAP3430_AUTO_CAM (1 << 0)		#define OMAP3430_AUTO_CAM_MASK (1 << 0)
	#define OMAP3430_AUTO_CAM_SHIFT 0		#define OMAP3430_AUTO_CAM_SHIFT 0

	/* CM_CLKSEL_CAM */		/* CM_CLKSEL_CAM */
	@@ -649,41 +649,41 @@
	#define OMAP3430_ST_MCBSP2_MASK (1 << 0)		#define OMAP3430_ST_MCBSP2_MASK (1 << 0)

	/* CM_AUTOIDLE_PER */		/* CM_AUTOIDLE_PER */
	#define OMAP3430_AUTO_GPIO6 (1 << 17)		#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
	#define OMAP3430_AUTO_GPIO6_SHIFT 17		#define OMAP3430_AUTO_GPIO6_SHIFT 17
	#define OMAP3430_AUTO_GPIO5 (1 << 16)		#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
	#define OMAP3430_AUTO_GPIO5_SHIFT 16		#define OMAP3430_AUTO_GPIO5_SHIFT 16
	#define OMAP3430_AUTO_GPIO4 (1 << 15)		#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
	#define OMAP3430_AUTO_GPIO4_SHIFT 15		#define OMAP3430_AUTO_GPIO4_SHIFT 15
	#define OMAP3430_AUTO_GPIO3 (1 << 14)		#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
	#define OMAP3430_AUTO_GPIO3_SHIFT 14		#define OMAP3430_AUTO_GPIO3_SHIFT 14
	#define OMAP3430_AUTO_GPIO2 (1 << 13)		#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
	#define OMAP3430_AUTO_GPIO2_SHIFT 13		#define OMAP3430_AUTO_GPIO2_SHIFT 13
	#define OMAP3430_AUTO_WDT3 (1 << 12)		#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
	#define OMAP3430_AUTO_WDT3_SHIFT 12		#define OMAP3430_AUTO_WDT3_SHIFT 12
	#define OMAP3430_AUTO_UART3 (1 << 11)		#define OMAP3430_AUTO_UART3_MASK (1 << 11)
	#define OMAP3430_AUTO_UART3_SHIFT 11		#define OMAP3430_AUTO_UART3_SHIFT 11
	#define OMAP3430_AUTO_GPT9 (1 << 10)		#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
	#define OMAP3430_AUTO_GPT9_SHIFT 10		#define OMAP3430_AUTO_GPT9_SHIFT 10
	#define OMAP3430_AUTO_GPT8 (1 << 9)		#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
	#define OMAP3430_AUTO_GPT8_SHIFT 9		#define OMAP3430_AUTO_GPT8_SHIFT 9
	#define OMAP3430_AUTO_GPT7 (1 << 8)		#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
	#define OMAP3430_AUTO_GPT7_SHIFT 8		#define OMAP3430_AUTO_GPT7_SHIFT 8
	#define OMAP3430_AUTO_GPT6 (1 << 7)		#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
	#define OMAP3430_AUTO_GPT6_SHIFT 7		#define OMAP3430_AUTO_GPT6_SHIFT 7
	#define OMAP3430_AUTO_GPT5 (1 << 6)		#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
	#define OMAP3430_AUTO_GPT5_SHIFT 6		#define OMAP3430_AUTO_GPT5_SHIFT 6
	#define OMAP3430_AUTO_GPT4 (1 << 5)		#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
	#define OMAP3430_AUTO_GPT4_SHIFT 5		#define OMAP3430_AUTO_GPT4_SHIFT 5
	#define OMAP3430_AUTO_GPT3 (1 << 4)		#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
	#define OMAP3430_AUTO_GPT3_SHIFT 4		#define OMAP3430_AUTO_GPT3_SHIFT 4
	#define OMAP3430_AUTO_GPT2 (1 << 3)		#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
	#define OMAP3430_AUTO_GPT2_SHIFT 3		#define OMAP3430_AUTO_GPT2_SHIFT 3
	#define OMAP3430_AUTO_MCBSP4 (1 << 2)		#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
	#define OMAP3430_AUTO_MCBSP4_SHIFT 2		#define OMAP3430_AUTO_MCBSP4_SHIFT 2
	#define OMAP3430_AUTO_MCBSP3 (1 << 1)		#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
	#define OMAP3430_AUTO_MCBSP3_SHIFT 1		#define OMAP3430_AUTO_MCBSP3_SHIFT 1
	#define OMAP3430_AUTO_MCBSP2 (1 << 0)		#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
	#define OMAP3430_AUTO_MCBSP2_SHIFT 0		#define OMAP3430_AUTO_MCBSP2_SHIFT 0

	/* CM_CLKSEL_PER */		/* CM_CLKSEL_PER */
	@@ -705,7 +705,7 @@
	#define OMAP3430_CLKSEL_GPT2_SHIFT 0		#define OMAP3430_CLKSEL_GPT2_SHIFT 0

	/* CM_SLEEPDEP_PER specific bits */		/* CM_SLEEPDEP_PER specific bits */
	#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)		#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)

	/* CM_CLKSTCTRL_PER */		/* CM_CLKSTCTRL_PER */
	#define OMAP3430_CLKTRCTRL_PER_SHIFT 0		#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
	@@ -755,10 +755,10 @@
	#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)		#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)

	/* CM_POLCTRL */		/* CM_POLCTRL */
	#define OMAP3430_CLKOUT2_POL (1 << 0)		#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)

	/* CM_IDLEST_NEON */		/* CM_IDLEST_NEON */
	#define OMAP3430_ST_NEON (1 << 0)		#define OMAP3430_ST_NEON_MASK (1 << 0)

	/* CM_CLKSTCTRL_NEON */		/* CM_CLKSTCTRL_NEON */
	#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0		#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0

arch/arm/mach-omap2/control.c

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -194,10 +194,11 @@ void omap3_clear_scratchpad_contents(void)
	u32 offset = 0;		u32 offset = 0;
	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);		v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &		if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
	OMAP3430_GLOBAL_COLD_RST) {		OMAP3430_GLOBAL_COLD_RST_MASK) {
	for ( ; offset <= max_offset; offset += 0x4)		for ( ; offset <= max_offset; offset += 0x4)
	__raw_writel(0x0, (v_addr + offset));		__raw_writel(0x0, (v_addr + offset));
	prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,		prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
			OMAP3430_GR_MOD,
	OMAP3_PRM_RSTST_OFFSET);		OMAP3_PRM_RSTST_OFFSET);
	}		}
	}		}

arch/arm/mach-omap2/pm34xx.c

+90 −88

Original line number	Original line	Diff line number	Diff line
	@@ -94,19 +94,20 @@ static void omap3_enable_io_chain(void)
	int timeout = 0;		int timeout = 0;

	if (omap_rev() >= OMAP3430_REV_ES3_1) {		if (omap_rev() >= OMAP3430_REV_ES3_1) {
	prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);		prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
			PM_WKEN);
	/* Do a readback to assure write has been done */		/* Do a readback to assure write has been done */
	prm_read_mod_reg(WKUP_MOD, PM_WKEN);		prm_read_mod_reg(WKUP_MOD, PM_WKEN);

	while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &		while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
	OMAP3430_ST_IO_CHAIN)) {		OMAP3430_ST_IO_CHAIN_MASK)) {
	timeout++;		timeout++;
	if (timeout > 1000) {		if (timeout > 1000) {
	printk(KERN_ERR "Wake up daisy chain "		printk(KERN_ERR "Wake up daisy chain "
	"activation failed.\n");		"activation failed.\n");
	return;		return;
	}		}
	prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,		prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
	WKUP_MOD, PM_WKST);		WKUP_MOD, PM_WKST);
	}		}
	}		}
	@@ -115,7 +116,8 @@ static void omap3_enable_io_chain(void)
	static void omap3_disable_io_chain(void)		static void omap3_disable_io_chain(void)
	{		{
	if (omap_rev() >= OMAP3430_REV_ES3_1)		if (omap_rev() >= OMAP3430_REV_ES3_1)
	prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);		prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
			PM_WKEN);
	}		}

	static void omap3_core_save_context(void)		static void omap3_core_save_context(void)
	@@ -278,7 +280,8 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
	irqstatus_mpu &= irqenable_mpu;		irqstatus_mpu &= irqenable_mpu;

	do {		do {
	if (irqstatus_mpu & (OMAP3430_WKUP_ST \| OMAP3430_IO_ST)) {		if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK \|
			OMAP3430_IO_ST_MASK)) {
	c = _prcm_int_handle_wakeup();		c = _prcm_int_handle_wakeup();

	/*		/*
	@@ -384,7 +387,7 @@ void omap_sram_idle(void)
	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);		core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
	if (per_next_state < PWRDM_POWER_ON \|\|		if (per_next_state < PWRDM_POWER_ON \|\|
	core_next_state < PWRDM_POWER_ON) {		core_next_state < PWRDM_POWER_ON) {
	prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);		prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
	omap3_enable_io_chain();		omap3_enable_io_chain();
	}		}

	@@ -458,7 +461,7 @@ void omap_sram_idle(void)
	omap_uart_resume_idle(0);		omap_uart_resume_idle(0);
	omap_uart_resume_idle(1);		omap_uart_resume_idle(1);
	if (core_next_state == PWRDM_POWER_OFF)		if (core_next_state == PWRDM_POWER_OFF)
	prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,		prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
	OMAP3430_GR_MOD,		OMAP3430_GR_MOD,
	OMAP3_PRM_VOLTCTRL_OFFSET);		OMAP3_PRM_VOLTCTRL_OFFSET);
	}		}
	@@ -476,9 +479,8 @@ void omap_sram_idle(void)
	}		}

	/* Disable IO-PAD and IO-CHAIN wakeup */		/* Disable IO-PAD and IO-CHAIN wakeup */
	if (per_next_state < PWRDM_POWER_ON \|\|		if (core_next_state < PWRDM_POWER_ON) {
	core_next_state < PWRDM_POWER_ON) {		prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
	prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
	omap3_disable_io_chain();		omap3_disable_io_chain();
	}		}

	@@ -699,9 +701,9 @@ static void __init omap3_iva_idle(void)
	return;		return;

	/* Reset IVA2 */		/* Reset IVA2 */
	prm_write_mod_reg(OMAP3430_RST1_IVA2 \|		prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK \|
	OMAP3430_RST2_IVA2 \|		OMAP3430_RST2_IVA2_MASK \|
	OMAP3430_RST3_IVA2,		OMAP3430_RST3_IVA2_MASK,
	OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);		OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);

	/* Enable IVA2 clock */		/* Enable IVA2 clock */
	@@ -719,9 +721,9 @@ static void __init omap3_iva_idle(void)
	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);		cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);

	/* Reset IVA2 */		/* Reset IVA2 */
	prm_write_mod_reg(OMAP3430_RST1_IVA2 \|		prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK \|
	OMAP3430_RST2_IVA2 \|		OMAP3430_RST2_IVA2_MASK \|
	OMAP3430_RST3_IVA2,		OMAP3430_RST3_IVA2_MASK,
	OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);		OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
	}		}

	@@ -743,8 +745,8 @@ static void __init omap3_d2d_idle(void)
	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);		omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);

	/* reset modem */		/* reset modem */
	prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON \|		prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK \|
	OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,		OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
	CORE_MOD, OMAP2_RM_RSTCTRL);		CORE_MOD, OMAP2_RM_RSTCTRL);
	prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);		prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
	}		}
	@@ -770,97 +772,97 @@ static void __init prcm_setup_regs(void)
	* Note that in the long run this should be done by clockfw		* Note that in the long run this should be done by clockfw
	*/		*/
	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_MODEM \|		OMAP3430_AUTO_MODEM_MASK \|
	OMAP3430ES2_AUTO_MMC3 \|		OMAP3430ES2_AUTO_MMC3_MASK \|
	OMAP3430ES2_AUTO_ICR \|		OMAP3430ES2_AUTO_ICR_MASK \|
	OMAP3430_AUTO_AES2 \|		OMAP3430_AUTO_AES2_MASK \|
	OMAP3430_AUTO_SHA12 \|		OMAP3430_AUTO_SHA12_MASK \|
	OMAP3430_AUTO_DES2 \|		OMAP3430_AUTO_DES2_MASK \|
	OMAP3430_AUTO_MMC2 \|		OMAP3430_AUTO_MMC2_MASK \|
	OMAP3430_AUTO_MMC1 \|		OMAP3430_AUTO_MMC1_MASK \|
	OMAP3430_AUTO_MSPRO \|		OMAP3430_AUTO_MSPRO_MASK \|
	OMAP3430_AUTO_HDQ \|		OMAP3430_AUTO_HDQ_MASK \|
	OMAP3430_AUTO_MCSPI4 \|		OMAP3430_AUTO_MCSPI4_MASK \|
	OMAP3430_AUTO_MCSPI3 \|		OMAP3430_AUTO_MCSPI3_MASK \|
	OMAP3430_AUTO_MCSPI2 \|		OMAP3430_AUTO_MCSPI2_MASK \|
	OMAP3430_AUTO_MCSPI1 \|		OMAP3430_AUTO_MCSPI1_MASK \|
	OMAP3430_AUTO_I2C3 \|		OMAP3430_AUTO_I2C3_MASK \|
	OMAP3430_AUTO_I2C2 \|		OMAP3430_AUTO_I2C2_MASK \|
	OMAP3430_AUTO_I2C1 \|		OMAP3430_AUTO_I2C1_MASK \|
	OMAP3430_AUTO_UART2 \|		OMAP3430_AUTO_UART2_MASK \|
	OMAP3430_AUTO_UART1 \|		OMAP3430_AUTO_UART1_MASK \|
	OMAP3430_AUTO_GPT11 \|		OMAP3430_AUTO_GPT11_MASK \|
	OMAP3430_AUTO_GPT10 \|		OMAP3430_AUTO_GPT10_MASK \|
	OMAP3430_AUTO_MCBSP5 \|		OMAP3430_AUTO_MCBSP5_MASK \|
	OMAP3430_AUTO_MCBSP1 \|		OMAP3430_AUTO_MCBSP1_MASK \|
	OMAP3430ES1_AUTO_FAC \| /* This is es1 only */		OMAP3430ES1_AUTO_FAC_MASK \| /* This is es1 only */
	OMAP3430_AUTO_MAILBOXES \|		OMAP3430_AUTO_MAILBOXES_MASK \|
	OMAP3430_AUTO_OMAPCTRL \|		OMAP3430_AUTO_OMAPCTRL_MASK \|
	OMAP3430ES1_AUTO_FSHOSTUSB \|		OMAP3430ES1_AUTO_FSHOSTUSB_MASK \|
	OMAP3430_AUTO_HSOTGUSB \|		OMAP3430_AUTO_HSOTGUSB_MASK \|
	OMAP3430_AUTO_SAD2D \|		OMAP3430_AUTO_SAD2D_MASK \|
	OMAP3430_AUTO_SSI,		OMAP3430_AUTO_SSI_MASK,
	CORE_MOD, CM_AUTOIDLE1);		CORE_MOD, CM_AUTOIDLE1);

	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_PKA \|		OMAP3430_AUTO_PKA_MASK \|
	OMAP3430_AUTO_AES1 \|		OMAP3430_AUTO_AES1_MASK \|
	OMAP3430_AUTO_RNG \|		OMAP3430_AUTO_RNG_MASK \|
	OMAP3430_AUTO_SHA11 \|		OMAP3430_AUTO_SHA11_MASK \|
	OMAP3430_AUTO_DES1,		OMAP3430_AUTO_DES1_MASK,
	CORE_MOD, CM_AUTOIDLE2);		CORE_MOD, CM_AUTOIDLE2);

	if (omap_rev() > OMAP3430_REV_ES1_0) {		if (omap_rev() > OMAP3430_REV_ES1_0) {
	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_MAD2D \|		OMAP3430_AUTO_MAD2D_MASK \|
	OMAP3430ES2_AUTO_USBTLL,		OMAP3430ES2_AUTO_USBTLL_MASK,
	CORE_MOD, CM_AUTOIDLE3);		CORE_MOD, CM_AUTOIDLE3);
	}		}

	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_WDT2 \|		OMAP3430_AUTO_WDT2_MASK \|
	OMAP3430_AUTO_WDT1 \|		OMAP3430_AUTO_WDT1_MASK \|
	OMAP3430_AUTO_GPIO1 \|		OMAP3430_AUTO_GPIO1_MASK \|
	OMAP3430_AUTO_32KSYNC \|		OMAP3430_AUTO_32KSYNC_MASK \|
	OMAP3430_AUTO_GPT12 \|		OMAP3430_AUTO_GPT12_MASK \|
	OMAP3430_AUTO_GPT1 ,		OMAP3430_AUTO_GPT1_MASK,
	WKUP_MOD, CM_AUTOIDLE);		WKUP_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_DSS,		OMAP3430_AUTO_DSS_MASK,
	OMAP3430_DSS_MOD,		OMAP3430_DSS_MOD,
	CM_AUTOIDLE);		CM_AUTOIDLE);

	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_CAM,		OMAP3430_AUTO_CAM_MASK,
	OMAP3430_CAM_MOD,		OMAP3430_CAM_MOD,
	CM_AUTOIDLE);		CM_AUTOIDLE);

	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430_AUTO_GPIO6 \|		OMAP3430_AUTO_GPIO6_MASK \|
	OMAP3430_AUTO_GPIO5 \|		OMAP3430_AUTO_GPIO5_MASK \|
	OMAP3430_AUTO_GPIO4 \|		OMAP3430_AUTO_GPIO4_MASK \|
	OMAP3430_AUTO_GPIO3 \|		OMAP3430_AUTO_GPIO3_MASK \|
	OMAP3430_AUTO_GPIO2 \|		OMAP3430_AUTO_GPIO2_MASK \|
	OMAP3430_AUTO_WDT3 \|		OMAP3430_AUTO_WDT3_MASK \|
	OMAP3430_AUTO_UART3 \|		OMAP3430_AUTO_UART3_MASK \|
	OMAP3430_AUTO_GPT9 \|		OMAP3430_AUTO_GPT9_MASK \|
	OMAP3430_AUTO_GPT8 \|		OMAP3430_AUTO_GPT8_MASK \|
	OMAP3430_AUTO_GPT7 \|		OMAP3430_AUTO_GPT7_MASK \|
	OMAP3430_AUTO_GPT6 \|		OMAP3430_AUTO_GPT6_MASK \|
	OMAP3430_AUTO_GPT5 \|		OMAP3430_AUTO_GPT5_MASK \|
	OMAP3430_AUTO_GPT4 \|		OMAP3430_AUTO_GPT4_MASK \|
	OMAP3430_AUTO_GPT3 \|		OMAP3430_AUTO_GPT3_MASK \|
	OMAP3430_AUTO_GPT2 \|		OMAP3430_AUTO_GPT2_MASK \|
	OMAP3430_AUTO_MCBSP4 \|		OMAP3430_AUTO_MCBSP4_MASK \|
	OMAP3430_AUTO_MCBSP3 \|		OMAP3430_AUTO_MCBSP3_MASK \|
	OMAP3430_AUTO_MCBSP2,		OMAP3430_AUTO_MCBSP2_MASK,
	OMAP3430_PER_MOD,		OMAP3430_PER_MOD,
	CM_AUTOIDLE);		CM_AUTOIDLE);

	if (omap_rev() > OMAP3430_REV_ES1_0) {		if (omap_rev() > OMAP3430_REV_ES1_0) {
	cm_write_mod_reg(		cm_write_mod_reg(
	OMAP3430ES2_AUTO_USBHOST,		OMAP3430ES2_AUTO_USBHOST_MASK,
	OMAP3430ES2_USBHOST_MOD,		OMAP3430ES2_USBHOST_MOD,
	CM_AUTOIDLE);		CM_AUTOIDLE);
	}		}
	@@ -895,7 +897,7 @@ static void __init prcm_setup_regs(void)
	OMAP3_PRM_CLKSRC_CTRL_OFFSET);		OMAP3_PRM_CLKSRC_CTRL_OFFSET);

	/* setup wakup source */		/* setup wakup source */
	prm_write_mod_reg(OMAP3430_EN_IO \| OMAP3430_EN_GPIO1 \|		prm_write_mod_reg(OMAP3430_EN_IO_MASK \| OMAP3430_EN_GPIO1 \|
	OMAP3430_EN_GPT1 \| OMAP3430_EN_GPT12,		OMAP3430_EN_GPT1 \| OMAP3430_EN_GPT12,
	WKUP_MOD, PM_WKEN);		WKUP_MOD, PM_WKEN);
	/* No need to write EN_IO, that is always enabled */		/* No need to write EN_IO, that is always enabled */
	@@ -904,11 +906,11 @@ static void __init prcm_setup_regs(void)
	WKUP_MOD, OMAP3430_PM_MPUGRPSEL);		WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
	/* For some reason IO doesn't generate wakeup event even if		/* For some reason IO doesn't generate wakeup event even if
	* it is selected to mpu wakeup goup */		* it is selected to mpu wakeup goup */
	prm_write_mod_reg(OMAP3430_IO_EN \| OMAP3430_WKUP_EN,		prm_write_mod_reg(OMAP3430_IO_EN_MASK \| OMAP3430_WKUP_EN_MASK,
	OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);		OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);

	/* Enable PM_WKEN to support DSS LPR */		/* Enable PM_WKEN to support DSS LPR */
	prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS,		prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
	OMAP3430_DSS_MOD, PM_WKEN);		OMAP3430_DSS_MOD, PM_WKEN);

	/* Enable wakeups in PER */		/* Enable wakeups in PER */
	@@ -919,9 +921,9 @@ static void __init prcm_setup_regs(void)
	OMAP3430_EN_MCBSP4,		OMAP3430_EN_MCBSP4,
	OMAP3430_PER_MOD, PM_WKEN);		OMAP3430_PER_MOD, PM_WKEN);
	/* and allow them to wake up MPU */		/* and allow them to wake up MPU */
	prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 \| OMAP3430_EN_GPIO3 \|		prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK \| OMAP3430_EN_GPIO3 \|
	OMAP3430_GRPSEL_GPIO4 \| OMAP3430_EN_GPIO5 \|		OMAP3430_GRPSEL_GPIO4_MASK \| OMAP3430_EN_GPIO5 \|
	OMAP3430_GRPSEL_GPIO6 \| OMAP3430_EN_UART3 \|		OMAP3430_GRPSEL_GPIO6_MASK \| OMAP3430_EN_UART3 \|
	OMAP3430_EN_MCBSP2 \| OMAP3430_EN_MCBSP3 \|		OMAP3430_EN_MCBSP2 \| OMAP3430_EN_MCBSP3 \|
	OMAP3430_EN_MCBSP4,		OMAP3430_EN_MCBSP4,
	OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);		OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);

arch/arm/mach-omap2/powerdomain.c

+13 −11

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arch/arm/mach-omap2/prm-regbits-34xx.h

+180 −180

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