Loading drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +3 −7 Original line number Diff line number Diff line Loading @@ -259,15 +259,11 @@ static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl, dsi_ctrl->cell_index, op_state); rc = -EINVAL; } else if (state->power_state == DSI_CTRL_POWER_VREG_ON) { if ((state->cmd_engine_state == DSI_CTRL_ENGINE_ON) || (state->vid_engine_state == DSI_CTRL_ENGINE_ON) || (state->controller_state == DSI_CTRL_ENGINE_ON)) { pr_debug("[%d]State error: op=%d: %d, %d, %d\n", if (state->vid_engine_state == DSI_CTRL_ENGINE_ON) { pr_debug("[%d]State error: op=%d: %d\n", dsi_ctrl->cell_index, op_state, state->cmd_engine_state, state->vid_engine_state, state->controller_state); state->vid_engine_state); rc = -EINVAL; } } Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +10 −0 Original line number Diff line number Diff line Loading @@ -3113,6 +3113,11 @@ int dsi_display_post_enable(struct dsi_display *display) pr_err("[%s] panel post-enable failed, rc=%d\n", display->name, rc); /* remove the clk vote for CMD mode panels */ if (display->config.panel_mode == DSI_OP_CMD_MODE) dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF); mutex_unlock(&display->display_lock); return rc; } Loading @@ -3128,6 +3133,11 @@ int dsi_display_pre_disable(struct dsi_display *display) mutex_lock(&display->display_lock); /* enable the clk vote for CMD mode panels */ if (display->config.panel_mode == DSI_OP_CMD_MODE) dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); rc = dsi_panel_pre_disable(display->panel); if (rc) pr_err("[%s] panel pre-disable failed, rc=%d\n", Loading drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +0 −32 Original line number Diff line number Diff line Loading @@ -791,23 +791,12 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, bool skip_validation) { int rc = 0; struct dsi_clk_ctrl_info clk_info; if (!phy || !config) { pr_err("Invalid params\n"); return -EINVAL; } clk_info.client = DSI_CLK_REQ_DSI_CLIENT; clk_info.clk_type = DSI_CORE_CLK; clk_info.clk_state = DSI_CLK_ON; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) { pr_err("failed to enable DSI core clocks\n"); return rc; } mutex_lock(&phy->phy_lock); if (!skip_validation) Loading Loading @@ -839,10 +828,6 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, error: mutex_unlock(&phy->phy_lock); clk_info.clk_state = DSI_CLK_OFF; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) pr_err("failed to disable DSI core clocks\n"); return rc; } Loading @@ -855,34 +840,17 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, int dsi_phy_disable(struct msm_dsi_phy *phy) { int rc = 0; struct dsi_clk_ctrl_info clk_info; if (!phy) { pr_err("Invalid params\n"); return -EINVAL; } clk_info.client = DSI_CLK_REQ_DSI_CLIENT; clk_info.clk_type = DSI_CORE_CLK; clk_info.clk_state = DSI_CLK_ON; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) { pr_err("failed to enable DSI core clocks\n"); return rc; } mutex_lock(&phy->phy_lock); dsi_phy_disable_hw(phy); phy->dsi_phy_state = DSI_PHY_ENGINE_OFF; mutex_unlock(&phy->phy_lock); clk_info.clk_state = DSI_CLK_OFF; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) pr_err("failed to disable DSI core clocks\n"); return rc; } Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +3 −7 Original line number Diff line number Diff line Loading @@ -259,15 +259,11 @@ static int dsi_ctrl_check_state(struct dsi_ctrl *dsi_ctrl, dsi_ctrl->cell_index, op_state); rc = -EINVAL; } else if (state->power_state == DSI_CTRL_POWER_VREG_ON) { if ((state->cmd_engine_state == DSI_CTRL_ENGINE_ON) || (state->vid_engine_state == DSI_CTRL_ENGINE_ON) || (state->controller_state == DSI_CTRL_ENGINE_ON)) { pr_debug("[%d]State error: op=%d: %d, %d, %d\n", if (state->vid_engine_state == DSI_CTRL_ENGINE_ON) { pr_debug("[%d]State error: op=%d: %d\n", dsi_ctrl->cell_index, op_state, state->cmd_engine_state, state->vid_engine_state, state->controller_state); state->vid_engine_state); rc = -EINVAL; } } Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +10 −0 Original line number Diff line number Diff line Loading @@ -3113,6 +3113,11 @@ int dsi_display_post_enable(struct dsi_display *display) pr_err("[%s] panel post-enable failed, rc=%d\n", display->name, rc); /* remove the clk vote for CMD mode panels */ if (display->config.panel_mode == DSI_OP_CMD_MODE) dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF); mutex_unlock(&display->display_lock); return rc; } Loading @@ -3128,6 +3133,11 @@ int dsi_display_pre_disable(struct dsi_display *display) mutex_lock(&display->display_lock); /* enable the clk vote for CMD mode panels */ if (display->config.panel_mode == DSI_OP_CMD_MODE) dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); rc = dsi_panel_pre_disable(display->panel); if (rc) pr_err("[%s] panel pre-disable failed, rc=%d\n", Loading
drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +0 −32 Original line number Diff line number Diff line Loading @@ -791,23 +791,12 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, bool skip_validation) { int rc = 0; struct dsi_clk_ctrl_info clk_info; if (!phy || !config) { pr_err("Invalid params\n"); return -EINVAL; } clk_info.client = DSI_CLK_REQ_DSI_CLIENT; clk_info.clk_type = DSI_CORE_CLK; clk_info.clk_state = DSI_CLK_ON; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) { pr_err("failed to enable DSI core clocks\n"); return rc; } mutex_lock(&phy->phy_lock); if (!skip_validation) Loading Loading @@ -839,10 +828,6 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, error: mutex_unlock(&phy->phy_lock); clk_info.clk_state = DSI_CLK_OFF; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) pr_err("failed to disable DSI core clocks\n"); return rc; } Loading @@ -855,34 +840,17 @@ int dsi_phy_enable(struct msm_dsi_phy *phy, int dsi_phy_disable(struct msm_dsi_phy *phy) { int rc = 0; struct dsi_clk_ctrl_info clk_info; if (!phy) { pr_err("Invalid params\n"); return -EINVAL; } clk_info.client = DSI_CLK_REQ_DSI_CLIENT; clk_info.clk_type = DSI_CORE_CLK; clk_info.clk_state = DSI_CLK_ON; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) { pr_err("failed to enable DSI core clocks\n"); return rc; } mutex_lock(&phy->phy_lock); dsi_phy_disable_hw(phy); phy->dsi_phy_state = DSI_PHY_ENGINE_OFF; mutex_unlock(&phy->phy_lock); clk_info.clk_state = DSI_CLK_OFF; rc = phy->clk_cb.dsi_clk_cb(phy->clk_cb.priv, clk_info); if (rc) pr_err("failed to disable DSI core clocks\n"); return rc; } Loading