Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2af1a29d authored by Aaro Koskinen's avatar Aaro Koskinen Committed by Greg Kroah-Hartman
Browse files

staging: xgifb: move XGINew_RAMType into vb_device_info 



The RAM type is device specific, so move it into vb_device_info.

Signed-off-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Reviewed-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent f2df8c09

drivers/staging/xgifb/vb_init.c

+71 −57
Original line number Diff line number Diff line
@@ -37,8 +37,6 @@ static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = { 
	{ 2, 12,  9,  8, 0x35},

	{ 2, 12,  8,  4, 0x31} };



static int XGINew_RAMType;



static unsigned char

XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,

		       struct vb_device_info *pVBInfo)
@@ -112,14 +110,18 @@ static void XGINew_DDR1x_MRS_340(unsigned long P3c4, 
	}



	udelay(60);

	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */

	xgifb_reg_set(P3c4,

		      0x18,

		      pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */

	xgifb_reg_set(P3c4, 0x19, 0x01);

	xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);

	xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);

	mdelay(1);

	xgifb_reg_set(P3c4, 0x1B, 0x03);

	udelay(500);

	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */

	xgifb_reg_set(P3c4,

		      0x18,

		      pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */

	xgifb_reg_set(P3c4, 0x19, 0x00);

	xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);

	xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
@@ -132,23 +134,23 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, 


	xgifb_reg_set(pVBInfo->P3c4,

		      0x28,

		      pVBInfo->MCLKData[XGINew_RAMType].SR28);

		      pVBInfo->MCLKData[pVBInfo->ram_type].SR28);

	xgifb_reg_set(pVBInfo->P3c4,

		      0x29,

		      pVBInfo->MCLKData[XGINew_RAMType].SR29);

		      pVBInfo->MCLKData[pVBInfo->ram_type].SR29);

	xgifb_reg_set(pVBInfo->P3c4,

		      0x2A,

		      pVBInfo->MCLKData[XGINew_RAMType].SR2A);

		      pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);



	xgifb_reg_set(pVBInfo->P3c4,

		      0x2E,

		      pVBInfo->ECLKData[XGINew_RAMType].SR2E);

		      pVBInfo->ECLKData[pVBInfo->ram_type].SR2E);

	xgifb_reg_set(pVBInfo->P3c4,

		      0x2F,

		      pVBInfo->ECLKData[XGINew_RAMType].SR2F);

		      pVBInfo->ECLKData[pVBInfo->ram_type].SR2F);

	xgifb_reg_set(pVBInfo->P3c4,

		      0x30,

		      pVBInfo->ECLKData[XGINew_RAMType].SR30);

		      pVBInfo->ECLKData[pVBInfo->ram_type].SR30);



	/* [Vicent] 2004/07/07,

	 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
@@ -156,12 +158,12 @@ static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, 
	 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,

	 * Set SR32 D[1:0] = 10b */

	if (HwDeviceExtension->jChipType == XG42) {

		if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&

		    (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&

		    (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&

		      (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||

		     ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&

		      (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))

		if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&

		    (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&

		    (((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&

		      (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||

		     ((pVBInfo->ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&

		      (pVBInfo->ECLKData[pVBInfo->ram_type].SR2F == 0x01))))

			xgifb_reg_set(pVBInfo->P3c4,

				      0x32,

				      ((unsigned char) xgifb_reg_get(
@@ -174,8 +176,7 @@ static void XGINew_DDRII_Bootup_XG27( 
			unsigned long P3c4, struct vb_device_info *pVBInfo)

{

	unsigned long P3d4 = P3c4 + 0x10;

	XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,

						      pVBInfo);

	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);

	XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);



	/* Set Double Frequency */
@@ -250,8 +251,7 @@ static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension, 
{

	unsigned long P3d4 = P3c4 + 0x10;



	XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,

						      pVBInfo);

	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);

	XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);



	xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
@@ -307,7 +307,9 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, 
	xgifb_reg_set(P3c4, 0x16, 0x00);

	xgifb_reg_set(P3c4, 0x16, 0x80);

	udelay(60);

	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */

	xgifb_reg_set(P3c4,

		      0x18,

		      pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */

	/* xgifb_reg_set(P3c4, 0x18, 0x31); */

	xgifb_reg_set(P3c4, 0x19, 0x01);

	xgifb_reg_set(P3c4, 0x16, 0x03);
@@ -316,7 +318,9 @@ static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, 
	xgifb_reg_set(P3c4, 0x1B, 0x03);

	udelay(500);

	/* xgifb_reg_set(P3c4, 0x18, 0x31); */

	xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */

	xgifb_reg_set(P3c4,

		      0x18,

		      pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */

	xgifb_reg_set(P3c4, 0x19, 0x00);

	xgifb_reg_set(P3c4, 0x16, 0x03);

	xgifb_reg_set(P3c4, 0x16, 0x83);
@@ -333,13 +337,13 @@ static void XGINew_DDR1x_DefaultRegister( 
		XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);

		xgifb_reg_set(P3d4,

			      0x82,

			      pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */

			      pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */

		xgifb_reg_set(P3d4,

			      0x85,

			      pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */

			      pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */

		xgifb_reg_set(P3d4,

			      0x86,

			      pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */

			      pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */



		xgifb_reg_set(P3d4, 0x98, 0x01);

		xgifb_reg_set(P3d4, 0x9A, 0x02);
@@ -354,15 +358,15 @@ static void XGINew_DDR1x_DefaultRegister( 
			/* CR82 */

			xgifb_reg_set(P3d4,

				      0x82,

				      pVBInfo->CR40[11][XGINew_RAMType]);

				      pVBInfo->CR40[11][pVBInfo->ram_type]);

			/* CR85 */

			xgifb_reg_set(P3d4,

				      0x85,

				      pVBInfo->CR40[12][XGINew_RAMType]);

				      pVBInfo->CR40[12][pVBInfo->ram_type]);

			/* CR86 */

			xgifb_reg_set(P3d4,

				      0x86,

				      pVBInfo->CR40[13][XGINew_RAMType]);

				      pVBInfo->CR40[13][pVBInfo->ram_type]);

			break;

		default:

			xgifb_reg_set(P3d4, 0x82, 0x88);
@@ -373,7 +377,7 @@ static void XGINew_DDR1x_DefaultRegister( 
			xgifb_reg_get(P3d4, 0x86);

			xgifb_reg_set(P3d4,

				      0x86,

				      pVBInfo->CR40[13][XGINew_RAMType]);

				      pVBInfo->CR40[13][pVBInfo->ram_type]);

			xgifb_reg_set(P3d4, 0x82, 0x77);

			xgifb_reg_set(P3d4, 0x85, 0x00);
@@ -386,11 +390,11 @@ static void XGINew_DDR1x_DefaultRegister( 
			/* CR85 */

			xgifb_reg_set(P3d4,

				      0x85,

				      pVBInfo->CR40[12][XGINew_RAMType]);

				      pVBInfo->CR40[12][pVBInfo->ram_type]);

			/* CR82 */

			xgifb_reg_set(P3d4,

				      0x82,

				      pVBInfo->CR40[11][XGINew_RAMType]);

				      pVBInfo->CR40[11][pVBInfo->ram_type]);

			break;

		}
@@ -415,16 +419,18 @@ static void XGINew_DDR2_DefaultRegister( 
	xgifb_reg_set(P3d4, 0x86, 0x88);

	xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */

	/* CR86 */

	xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);

	xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);

	xgifb_reg_set(P3d4, 0x82, 0x77);

	xgifb_reg_set(P3d4, 0x85, 0x00);

	xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */

	xgifb_reg_set(P3d4, 0x85, 0x88);

	xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */

	xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */

	xgifb_reg_set(P3d4,

		      0x85,

		      pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */

	if (HwDeviceExtension->jChipType == XG27)

		/* CR82 */

		xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);

		xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);

	else

		xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
@@ -444,15 +450,15 @@ static void XGINew_SetDRAMDefaultRegister340( 


	unsigned long P3d4 = Port, P3c4 = Port - 0x10;



	xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);

	xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);

	xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);

	xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);

	xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);

	xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);

	xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);

	xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);



	temp2 = 0;

	for (i = 0; i < 4; i++) {

		/* CR6B DQS fine tune delay */

		temp = pVBInfo->CR6B[XGINew_RAMType][i];

		temp = pVBInfo->CR6B[pVBInfo->ram_type][i];

		for (j = 0; j < 4; j++) {

			temp1 = ((temp >> (2 * j)) & 0x03) << 2;

			temp2 |= temp1;
@@ -467,7 +473,7 @@ static void XGINew_SetDRAMDefaultRegister340( 
	temp2 = 0;

	for (i = 0; i < 4; i++) {

		/* CR6E DQM fine tune delay */

		temp = pVBInfo->CR6E[XGINew_RAMType][i];

		temp = pVBInfo->CR6E[pVBInfo->ram_type][i];

		for (j = 0; j < 4; j++) {

			temp1 = ((temp >> (2 * j)) & 0x03) << 2;

			temp2 |= temp1;
@@ -486,7 +492,7 @@ static void XGINew_SetDRAMDefaultRegister340( 
		temp2 = 0;

		for (i = 0; i < 8; i++) {

			/* CR6F DQ fine tune delay */

			temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];

			temp = pVBInfo->CR6F[pVBInfo->ram_type][8 * k + i];

			for (j = 0; j < 4; j++) {

				temp1 = (temp >> (2 * j)) & 0x03;

				temp2 |= temp1;
@@ -500,12 +506,16 @@ static void XGINew_SetDRAMDefaultRegister340( 
		temp3 += 0x01;

	}



	xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */

	xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */

	xgifb_reg_set(P3d4,

		      0x80,

		      pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */

	xgifb_reg_set(P3d4,

		      0x81,

		      pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */



	temp2 = 0x80;

	/* CR89 terminator type select */

	temp = pVBInfo->CR89[XGINew_RAMType][0];

	temp = pVBInfo->CR89[pVBInfo->ram_type][0];

	for (j = 0; j < 4; j++) {

		temp1 = (temp >> (2 * j)) & 0x03;

		temp2 |= temp1;
@@ -515,45 +525,49 @@ static void XGINew_SetDRAMDefaultRegister340( 
		temp2 += 0x10;

	}



	temp = pVBInfo->CR89[XGINew_RAMType][1];

	temp = pVBInfo->CR89[pVBInfo->ram_type][1];

	temp1 = temp & 0x03;

	temp2 |= temp1;

	xgifb_reg_set(P3d4, 0x89, temp2);



	temp = pVBInfo->CR40[3][XGINew_RAMType];

	temp = pVBInfo->CR40[3][pVBInfo->ram_type];

	temp1 = temp & 0x0F;

	temp2 = (temp >> 4) & 0x07;

	temp3 = temp & 0x80;

	xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */

	xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */

	xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */

	xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */

	xgifb_reg_set(P3d4,

		      0x41,

		      pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */



	if (HwDeviceExtension->jChipType == XG27)

		xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */



	for (j = 0; j <= 6; j++) /* CR90 - CR96 */

		xgifb_reg_set(P3d4, (0x90 + j),

				pVBInfo->CR40[14 + j][XGINew_RAMType]);

				pVBInfo->CR40[14 + j][pVBInfo->ram_type]);



	for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */

		xgifb_reg_set(P3d4, (0xC3 + j),

				pVBInfo->CR40[21 + j][XGINew_RAMType]);

				pVBInfo->CR40[21 + j][pVBInfo->ram_type]);



	for (j = 0; j < 2; j++) /* CR8A - CR8B */

		xgifb_reg_set(P3d4, (0x8A + j),

				pVBInfo->CR40[1 + j][XGINew_RAMType]);

				pVBInfo->CR40[1 + j][pVBInfo->ram_type]);



	if ((HwDeviceExtension->jChipType == XG41) ||

	    (HwDeviceExtension->jChipType == XG42))

		xgifb_reg_set(P3d4, 0x8C, 0x87);



	xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */

	xgifb_reg_set(P3d4,

		      0x59,

		      pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */



	xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */

	xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */

	xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */

	if (XGINew_RAMType) {

	if (pVBInfo->ram_type) {

		/* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */

		xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */

		if (HwDeviceExtension->jChipType == XG27)
@@ -571,7 +585,9 @@ static void XGINew_SetDRAMDefaultRegister340( 
		xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */

		XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);

	}

	xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */

	xgifb_reg_set(P3c4,

		      0x1B,

		      pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */

}



static void XGINew_SetDRAMSizingType(int index,
@@ -1552,8 +1568,7 @@ unsigned char XGIInitNew(struct pci_dev *pdev) 


	/* 3.SetMemoryClock



	 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,

						      pVBInfo);

	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);

	*/



	printk("11");
@@ -1754,8 +1769,7 @@ unsigned char XGIInitNew(struct pci_dev *pdev) 
	}

	printk("19");



	XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,

						      pVBInfo);

	pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);



	XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,

					 pVBInfo->P3d4,

drivers/staging/xgifb/vb_struct.h

+2 −0
Original line number Diff line number Diff line
@@ -392,6 +392,8 @@ struct vb_device_info { 
	struct XGI_StResInfoStruct   *StResInfo;

	struct XGI_ModeResInfoStruct *ModeResInfo;

	struct XGI_XG21CRT1Struct	  *UpdateCRT1;



	int ram_type;

};  /* _struct vb_device_info */



#endif /* _VB_STRUCT_ */