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Commit 2aba76f0 authored by Michael Williamson's avatar Michael Williamson Committed by Liam Girdwood
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audio: tlv320aic26: fix PLL register configuration 



The current PLL configuration code for the tlc320aic26 codec appears to assume a
hardcoded system clock of 12 MHz.  Use the clock value provided by the DAI_OPS
API for the calculation.

Tested using a MityDSP-L138 platform providing a 24.576 MHz clock.

Signed-off-by: default avatarMichael Williamson <michael.williamson@criticallink.com>
Acked-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: default avatarLiam Girdwood <lrg@ti.com>
parent 4a787a3f

sound/soc/codecs/tlv320aic26.c

+11 −3
Original line number Original line Diff line number Diff line
@@ -161,10 +161,18 @@ static int aic26_hw_params(struct snd_pcm_substream *substream, 
		dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;

		dev_dbg(&aic26->spi->dev, "bad format\n"); return -EINVAL;

	}

	}





	/* Configure PLL */

	/**

	 * Configure PLL

	 * fsref = (mclk * PLLM) / 2048

	 * where PLLM = J.DDDD (DDDD register ranges from 0 to 9999, decimal)

	 */

	pval = 1;

	pval = 1;

	jval = (fsref == 44100) ? 7 : 8;

	/* compute J portion of multiplier */

	dval = (fsref == 44100) ? 5264 : 1920;

	jval = fsref / (aic26->mclk / 2048);

	/* compute fractional DDDD component of multiplier */

	dval = fsref - (jval * (aic26->mclk / 2048));

	dval = (10000 * dval) / (aic26->mclk / 2048);

	dev_dbg(&aic26->spi->dev, "Setting PLLM to %d.%04d\n", jval, dval);

	qval = 0;

	qval = 0;

	reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;

	reg = 0x8000 | qval << 11 | pval << 8 | jval << 2;

	aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);

	aic26_reg_write(codec, AIC26_REG_PLL_PROG1, reg);