clk: mdss: add pll common block register settings for pll 1

One subset of pll common block setting registers need to be programmed
for both pll 0 and pll 1 to prevent current leakage.

Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>