Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2944a44d authored by Roland Stigge's avatar Roland Stigge Committed by David Woodhouse
Browse files

mtd: add LPC32xx SLC NAND driver 



This patch adds support for the SLC NAND controller inside the LPC32xx SoC.

[dwmw2: 21st century pedantry]

Signed-off-by: default avatarRoland Stigge <stigge@antcom.de>
Signed-off-by: default avatarArtem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent fdbad98d

Documentation/devicetree/bindings/mtd/lpc32xx-slc.txt

0 → 100644
+52 −0
Original line number Diff line number Diff line 
NXP LPC32xx SoC NAND SLC controller



Required properties:

- compatible: "nxp,lpc3220-slc"

- reg: Address and size of the controller

- nand-on-flash-bbt: Use bad block table on flash

- gpios: GPIO specification for NAND write protect



The following required properties are very controller specific. See the LPC32xx

User Manual:

- nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)

- nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)

(The following values are specified in Hz, to make them independent of actual

clock speed:)

- nxp,wwidth: Write pulse width (W_WIDTH)

- nxp,whold: Write hold time (W_HOLD)

- nxp,wsetup: Write setup time (W_SETUP)

- nxp,rwidth: Read pulse width (R_WIDTH)

- nxp,rhold: Read hold time (R_HOLD)

- nxp,rsetup: Read setup time (R_SETUP)



Optional subnodes:

- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt



Example:



	slc: flash@20020000 {

		compatible = "nxp,lpc3220-slc";

		reg = <0x20020000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		nxp,wdr-clks = <14>;

		nxp,wwidth = <40000000>;

		nxp,whold = <100000000>;

		nxp,wsetup = <100000000>;

		nxp,rdr-clks = <14>;

		nxp,rwidth = <40000000>;

		nxp,rhold = <66666666>;

		nxp,rsetup = <100000000>;

		nand-on-flash-bbt;

		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */



		mtd0@00000000 {

			label = "phy3250-boot";

			reg = <0x00000000 0x00064000>;

			read-only;

		};



		...



	};

drivers/mtd/nand/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -454,6 +454,17 @@ config MTD_NAND_PXA3xx 
	  This enables the driver for the NAND flash device found on

	  PXA3xx processors



config MTD_NAND_SLC_LPC32XX

	tristate "NXP LPC32xx SLC Controller"

	depends on ARCH_LPC32XX

	help

	  Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell

	  chips) NAND controller. This is the default for the PHYTEC 3250

	  reference board which contains a NAND256R3A2CZA6 chip.



	  Please check the actual NAND chip connected and its support

	  by the SLC NAND controller.



config MTD_NAND_CM_X270

	tristate "Support for NAND Flash on CM-X270 modules"

	depends on MACH_ARMCORE

drivers/mtd/nand/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o 
obj-$(CONFIG_MTD_NAND_FSL_ELBC)		+= fsl_elbc_nand.o

obj-$(CONFIG_MTD_NAND_FSL_IFC)		+= fsl_ifc_nand.o

obj-$(CONFIG_MTD_NAND_FSL_UPM)		+= fsl_upm.o

obj-$(CONFIG_MTD_NAND_SLC_LPC32XX)      += lpc32xx_slc.o

obj-$(CONFIG_MTD_NAND_SH_FLCTL)		+= sh_flctl.o

obj-$(CONFIG_MTD_NAND_MXC)		+= mxc_nand.o

obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o