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Commit 28da9ed6 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-fixes-2016-10-11' of... 

Merge tag 'drm-intel-next-fixes-2016-10-11' of git://anongit.freedesktop.org/drm-intel into drm-next

A big bunch of i915 fixes for drm-next / v4.9 merge window, with more
than half of them also cc: stable. We also continue to have more Fixes:
annotations for our fixes, which should help the backporters and
archeologists.

* tag 'drm-intel-next-fixes-2016-10-11' of git://anongit.freedesktop.org/drm-intel: (27 commits)
  drm/i915: Fix conflict resolution from backmerge of v4.8-rc8 to drm-next
  drm/i915/guc: Unwind GuC workqueue reservation if request construction fails
  drm/i915: Reset the breadcrumbs IRQ more carefully
  drm/i915: Force relocations via cpu if we run out of idle aperture
  drm/i915: Distinguish last emitted request from last submitted request
  drm/i915: Allow DP to work w/o EDID
  drm/i915: Move long hpd handling into the hotplug work
  drm/i915/execlists: Reinitialise context image after GPU hang
  drm/i915: Use correct index for backtracking HUNG semaphores
  drm/i915: Unalias obj->phys_handle and obj->userptr
  drm/i915: Just clear the mmiodebug before a register access
  drm/i915/gen9: only add the planes actually affected by ddb changes
  drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED
  drm/i915/bxt: Fix HDMI DPLL configuration
  drm/i915/gen9: fix the watermark res_blocks value
  drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations
  drm/i915/gen9: minimum scanlines for Y tile is not always 4
  drm/i915/gen9: fix the WaWmMemoryReadLatency implementation
  drm/i915/kbl: KBL also needs to run the SAGV code
  drm/i915: introduce intel_has_sagv()
  ...
parents b8985785 105f1a65

drivers/gpu/drm/i915/i915_drv.c

+11 −10
Original line number Diff line number Diff line
@@ -1786,15 +1786,6 @@ void i915_reset(struct drm_i915_private *dev_priv) 
		goto error;

	}



	/*

	 * rps/rc6 re-init is necessary to restore state lost after the

	 * reset and the re-install of gt irqs. Skip for ironlake per

	 * previous concerns that it doesn't respond well to some forms

	 * of re-init after reset.

	 */

	intel_sanitize_gt_powersave(dev_priv);

	intel_autoenable_gt_powersave(dev_priv);



wakeup:

	wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);

	return;
@@ -1872,7 +1863,17 @@ static int i915_pm_resume(struct device *kdev) 
/* freeze: before creating the hibernation_image */

static int i915_pm_freeze(struct device *kdev)

{

	return i915_pm_suspend(kdev);

	int ret;



	ret = i915_pm_suspend(kdev);

	if (ret)

		return ret;



	ret = i915_gem_freeze(kdev_to_i915(kdev));

	if (ret)

		return ret;



	return 0;

}



static int i915_pm_freeze_late(struct device *kdev)

drivers/gpu/drm/i915/i915_drv.h

+17 −18
Original line number Diff line number Diff line
@@ -1984,11 +1984,11 @@ struct drm_i915_private { 
	struct vlv_s0ix_state vlv_s0ix_state;



	enum {

		I915_SKL_SAGV_UNKNOWN = 0,

		I915_SKL_SAGV_DISABLED,

		I915_SKL_SAGV_ENABLED,

		I915_SKL_SAGV_NOT_CONTROLLED

	} skl_sagv_status;

		I915_SAGV_UNKNOWN = 0,

		I915_SAGV_DISABLED,

		I915_SAGV_ENABLED,

		I915_SAGV_NOT_CONTROLLED

	} sagv_status;



	struct {

		/*
@@ -2276,10 +2276,6 @@ struct drm_i915_gem_object { 
	/** Record of address bit 17 of each page at last unbind. */

	unsigned long *bit_17;



	union {

		/** for phy allocated objects */

		struct drm_dma_handle *phys_handle;



	struct i915_gem_userptr {

		uintptr_t ptr;

		unsigned read_only :1;
@@ -2290,7 +2286,9 @@ struct drm_i915_gem_object { 
		struct i915_mmu_object *mmu_object;

		struct work_struct *work;

	} userptr;

	};



	/** for phys allocated objects */

	struct drm_dma_handle *phys_handle;

};



static inline struct drm_i915_gem_object *
@@ -3076,6 +3074,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 
void i915_gem_load_init(struct drm_device *dev);

void i915_gem_load_cleanup(struct drm_device *dev);

void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);

int i915_gem_freeze(struct drm_i915_private *dev_priv);

int i915_gem_freeze_late(struct drm_i915_private *dev_priv);



void *i915_gem_object_alloc(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+23 −4
Original line number Diff line number Diff line
@@ -2616,8 +2616,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) 
	list_for_each_entry_continue(request, &engine->request_list, link)

		if (request->ctx == incomplete_ctx)

			reset_request(request);



	engine->i915->gt.active_engines &= ~intel_engine_flag(engine);

}



void i915_gem_reset(struct drm_i915_private *dev_priv)
@@ -2628,9 +2626,15 @@ void i915_gem_reset(struct drm_i915_private *dev_priv) 


	for_each_engine(engine, dev_priv)

		i915_gem_reset_engine(engine);

	mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);



	i915_gem_restore_fences(&dev_priv->drm);



	if (dev_priv->gt.awake) {

		intel_sanitize_gt_powersave(dev_priv);

		intel_enable_gt_powersave(dev_priv);

		if (INTEL_GEN(dev_priv) >= 6)

			gen6_rps_busy(dev_priv);

	}

}



static void nop_submit_request(struct drm_i915_gem_request *request)
@@ -4589,6 +4593,19 @@ void i915_gem_load_cleanup(struct drm_device *dev) 
	rcu_barrier();

}



int i915_gem_freeze(struct drm_i915_private *dev_priv)

{

	intel_runtime_pm_get(dev_priv);



	mutex_lock(&dev_priv->drm.struct_mutex);

	i915_gem_shrink_all(dev_priv);

	mutex_unlock(&dev_priv->drm.struct_mutex);



	intel_runtime_pm_put(dev_priv);



	return 0;

}



int i915_gem_freeze_late(struct drm_i915_private *dev_priv)

{

	struct drm_i915_gem_object *obj;
@@ -4612,7 +4629,8 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv) 
	 * the objects as well.

	 */



	i915_gem_shrink_all(dev_priv);

	mutex_lock(&dev_priv->drm.struct_mutex);

	i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);



	for (p = phases; *p; p++) {

		list_for_each_entry(obj, *p, global_list) {
@@ -4620,6 +4638,7 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv) 
			obj->base.write_domain = I915_GEM_DOMAIN_CPU;

		}

	}

	mutex_unlock(&dev_priv->drm.struct_mutex);



	return 0;

}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -451,8 +451,8 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, 
				 0, ggtt->mappable_end,

				 DRM_MM_SEARCH_DEFAULT,

				 DRM_MM_CREATE_DEFAULT);

			if (ret)

				return ERR_PTR(ret);

			if (ret) /* no inactive aperture space, use cpu reloc */

				return NULL;

		} else {

			ret = i915_vma_put_fence(vma);

			if (ret) {

drivers/gpu/drm/i915/i915_gem_request.c

+3 −2
Original line number Diff line number Diff line
@@ -328,6 +328,7 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) 


	switch (state) {

	case FENCE_COMPLETE:

		request->engine->last_submitted_seqno = request->fence.seqno;

		request->engine->submit_request(request);

		break;
@@ -641,8 +642,8 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) 
					     &request->submitq);



	request->emitted_jiffies = jiffies;

	request->previous_seqno = engine->last_submitted_seqno;

	engine->last_submitted_seqno = request->fence.seqno;

	request->previous_seqno = engine->last_pending_seqno;

	engine->last_pending_seqno = request->fence.seqno;

	i915_gem_active_set(&engine->last_request, request);

	list_add_tail(&request->link, &engine->request_list);

	list_add_tail(&request->ring_link, &ring->request_list);