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Commit 28af0a27 authored by Eric Anholt's avatar Eric Anholt Committed by Dave Airlie
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drm: G33-class hardware has a newer 965-style MCH (no DCC register). 



Fixes bad software fallback rendering in Mesa in dual-channel configurations.

d9a2470012588dc5313a5ac8bb2f03575af00e99

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 4f481ed2

drivers/gpu/drm/i915/i915_gem_tiling.c

+1 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
		 */

		swizzle_x = I915_BIT_6_SWIZZLE_NONE;

		swizzle_y = I915_BIT_6_SWIZZLE_NONE;

	} else if (!IS_I965G(dev) || IS_I965GM(dev)) {

	} else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {

		uint32_t dcc;



		/* On 915-945 and GM965, channel interleave by the CPU is