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Commit 288d2b5f authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

ARM: dts: msm: Update the CPU clock speedbin table for SDM845v2 



Allow running the L3 clock at 1593.6 MHz on SDM845v2 parts
with speedbin 1.

Change-Id: I6378cb9d4c34e2495a272f643360f374fed4139b
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent b7d8a0a0

arch/arm64/boot/dts/qcom/sdm845-v2.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -483,6 +483,23 @@ 
		<  1401600000 0x40340c49 0x00003a3a 0x2 13 >,

		<  1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;



	qcom,l3-speedbin1-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,

		<   480000000 0x50140219 0x00002020 0x1 3 >,

		<   576000000 0x5014031e 0x00002020 0x1 4 >,

		<   652800000 0x401c0422 0x00002020 0x1 5 >,

		<   748800000 0x401c0527 0x00002020 0x1 6 >,

		<   844800000 0x4024062c 0x00002323 0x2 7 >,

		<   940800000 0x40240731 0x00002727 0x2 8 >,

		<  1036800000 0x40240836 0x00002b2b 0x2 9 >,

		<  1132800000 0x402c093b 0x00002f2f 0x2 10 >,

		<  1209600000 0x402c0a3f 0x00003232 0x2 11 >,

		<  1305600000 0x40340b44 0x00003636 0x2 12 >,

		<  1401600000 0x40340c49 0x00003a3a 0x2 13 >,

		<  1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,

		<  1593600000 0x403c0e53 0x00004242 0x2 15 >;



	qcom,pwrcl-speedbin0-v0 =

		<   300000000 0x000c000f 0x00002020 0x1 1 >,

		<   403200000 0x500c0115 0x00002020 0x1 2 >,
@@ -566,6 +583,7 @@ 
		<  2707200000 0x40541e8d 0x00007171 0x2 31 >;



	qcom,l3-memacc-level-vc-bin0 = <8 13>;

	qcom,l3-memacc-level-vc-bin1 = <8 13>;



	qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;