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Commit 2861be21 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: gic: Use _no_log variants while accessing some registers"

parents 67138a4d c63401ef

drivers/irqchip/irq-gic.c

+29 −20
Original line number Diff line number Diff line
@@ -229,7 +229,7 @@ static void gic_unmask_irq(struct irq_data *d) 


static void gic_eoi_irq(struct irq_data *d)

{

	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);

	writel_relaxed_no_log(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);

}



static void gic_eoimode1_eoi_irq(struct irq_data *d)
@@ -340,8 +340,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 
	gic_lock_irqsave(flags);

	mask = 0xff << shift;

	bit = gic_cpu_map[cpu] << shift;

	val = readl_relaxed(reg) & ~mask;

	writel_relaxed(val | bit, reg);

	val = readl_relaxed_no_log(reg) & ~mask;

	writel_relaxed_no_log(val | bit, reg);

	gic_unlock_irqrestore(flags);



	return IRQ_SET_MASK_OK_DONE;
@@ -355,19 +355,21 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 
	void __iomem *cpu_base = gic_data_cpu_base(gic);



	do {

		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);

		irqstat = readl_relaxed_no_log(cpu_base + GIC_CPU_INTACK);

		irqnr = irqstat & GICC_IAR_INT_ID_MASK;



		if (likely(irqnr > 15 && irqnr < 1020)) {

			if (static_key_true(&supports_deactivate))

				writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);

				writel_relaxed_no_log(irqstat,

						cpu_base + GIC_CPU_EOI);

			handle_domain_irq(gic->domain, irqnr, regs);

			continue;

		}

		if (irqnr < 16) {

			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);

			writel_relaxed_no_log(irqstat, cpu_base + GIC_CPU_EOI);

			if (static_key_true(&supports_deactivate))

				writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);

				writel_relaxed_no_log(irqstat,

						cpu_base + GIC_CPU_DEACTIVATE);

#ifdef CONFIG_SMP

			/*

			 * Ensure any shared data written by the CPU sending
@@ -656,16 +658,18 @@ void gic_cpu_save(struct gic_chip_data *gic) 


	ptr = raw_cpu_ptr(gic->saved_ppi_enable);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)

		ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);

		ptr[i] = readl_relaxed_no_log(dist_base +

				GIC_DIST_ENABLE_SET + i * 4);



	ptr = raw_cpu_ptr(gic->saved_ppi_active);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)

		ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);

		ptr[i] = readl_relaxed_no_log(dist_base +

				GIC_DIST_ACTIVE_SET + i * 4);



	ptr = raw_cpu_ptr(gic->saved_ppi_conf);

	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)

		ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);



		ptr[i] = readl_relaxed_no_log(dist_base +

				GIC_DIST_CONFIG + i * 4);

}



void gic_cpu_restore(struct gic_chip_data *gic)
@@ -686,27 +690,31 @@ void gic_cpu_restore(struct gic_chip_data *gic) 


	ptr = raw_cpu_ptr(gic->saved_ppi_enable);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {

		writel_relaxed(GICD_INT_EN_CLR_X32,

		writel_relaxed_no_log(GICD_INT_EN_CLR_X32,

			       dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);

		writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);

		writel_relaxed_no_log(ptr[i], dist_base +

				GIC_DIST_ENABLE_SET + i * 4);

	}



	ptr = raw_cpu_ptr(gic->saved_ppi_active);

	for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {

		writel_relaxed(GICD_INT_EN_CLR_X32,

		writel_relaxed_no_log(GICD_INT_EN_CLR_X32,

			       dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);

		writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);

		writel_relaxed_no_log(ptr[i], dist_base +

				GIC_DIST_ACTIVE_SET + i * 4);

	}



	ptr = raw_cpu_ptr(gic->saved_ppi_conf);

	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)

		writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);

		writel_relaxed_no_log(ptr[i], dist_base +

				GIC_DIST_CONFIG + i * 4);



	for (i = 0; i < DIV_ROUND_UP(32, 4); i++)

		writel_relaxed(GICD_INT_DEF_PRI_X4,

		writel_relaxed_no_log(GICD_INT_DEF_PRI_X4,

					dist_base + GIC_DIST_PRI + i * 4);



	writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);

	writel_relaxed_no_log(GICC_INT_PRI_THRESHOLD,

				cpu_base + GIC_CPU_PRIMASK);

	gic_cpu_if_up(gic);

}
@@ -799,7 +807,7 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 


	if (unlikely(nr_cpu_ids == 1)) {

		/* Only one CPU? let's do a self-IPI... */

		writel_relaxed(2 << 24 | irq,

		writel_relaxed_no_log(2 << 24 | irq,

			       gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

		return;

	}
@@ -817,7 +825,8 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 
	dmb(ishst);



	/* this always happens on GIC0 */

	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);

	writel_relaxed_no_log(map << 16 | irq,

			gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);



	gic_unlock_irqrestore(flags);

}