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Commit 280fbb7c authored Jun 28, 2018 by Liangliang Lu

ARM: dts: msm: Update HS USB PHY parameters for HDK670



Update HS USB PHY parameters which can pass eye diagram test.

Change-Id: Ib79be129b127f3704413af42262af7e350690391
Signed-off-by: Liangliang Lu <luliang@codeaurora.org>

parent 7f551e7f

arch/arm64/boot/dts/qcom/sda670-hdk.dtsi

+43 −0

Original line number	Diff line number	Diff line
		@@ -61,3 +61,46 @@

		status = "ok";
		};

		&qusb_phy0 {
		qcom,qusb-phy-host-init-seq =
		/* <value reg_offset> */
		<0x23 0x210 /* PWR_CTRL1 */
		0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
		0x7c 0x18c /* PLL_CLOCK_INVERTERS */
		0x80 0x2c /* PLL_CMODE */
		0x0a 0x184 /* PLL_LOCK_DELAY */
		0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
		0x40 0x194 /* PLL_BIAS_CONTROL_1 */
		0x20 0x198 /* PLL_BIAS_CONTROL_2 */
		0x21 0x214 /* PWR_CTRL2 */
		0x00 0x220 /* IMP_CTRL1 */
		0x58 0x224 /* IMP_CTRL2 */
		0x77 0x240 /* TUNE1 */
		0x29 0x244 /* TUNE2 */
		0xca 0x248 /* TUNE3 */
		0x04 0x24c /* TUNE4 */
		0x03 0x250 /* TUNE5 */
		0x00 0x23c /* CHG_CTRL2 */
		0x22 0x210>; /* PWR_CTRL1 */
		qcom,qusb-phy-init-seq =
		/* <value reg_offset> */
		<0x23 0x210 /* PWR_CTRL1 */
		0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
		0x7c 0x18c /* PLL_CLOCK_INVERTERS */
		0x80 0x2c /* PLL_CMODE */
		0x0a 0x184 /* PLL_LOCK_DELAY */
		0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
		0x40 0x194 /* PLL_BIAS_CONTROL_1 */
		0x20 0x198 /* PLL_BIAS_CONTROL_2 */
		0x21 0x214 /* PWR_CTRL2 */
		0x25 0x220 /* IMP_CTRL1 */
		0x58 0x224 /* IMP_CTRL2 */
		0x65 0x240 /* TUNE1 */
		0x29 0x244 /* TUNE2 */
		0xca 0x248 /* TUNE3 */
		0x04 0x24c /* TUNE4 */
		0x03 0x250 /* TUNE5 */
		0x00 0x23c /* CHG_CTRL2 */
		0x22 0x210>; /* PWR_CTRL1 */
		};