Loading drivers/power/supply/qcom/smb-lib.c +16 −0 Original line number Diff line number Diff line Loading @@ -2404,6 +2404,22 @@ int smblib_set_prop_typec_power_role(struct smb_charger *chg, return -EINVAL; } if (power_role == UFP_EN_CMD_BIT) { /* disable PBS workaround when forcing sink mode */ rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0x0); if (rc < 0) { smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", rc); } } else { /* restore it back to 0xA5 */ rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0xA5); if (rc < 0) { smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", rc); } } rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, TYPEC_POWER_ROLE_CMD_MASK, power_role); if (rc < 0) { Loading drivers/power/supply/qcom/smb-reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -1018,6 +1018,8 @@ enum { #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0) #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1) #define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9) /* CHGR FREQ Peripheral registers */ #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50) Loading Loading
drivers/power/supply/qcom/smb-lib.c +16 −0 Original line number Diff line number Diff line Loading @@ -2404,6 +2404,22 @@ int smblib_set_prop_typec_power_role(struct smb_charger *chg, return -EINVAL; } if (power_role == UFP_EN_CMD_BIT) { /* disable PBS workaround when forcing sink mode */ rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0x0); if (rc < 0) { smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", rc); } } else { /* restore it back to 0xA5 */ rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0xA5); if (rc < 0) { smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", rc); } } rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, TYPEC_POWER_ROLE_CMD_MASK, power_role); if (rc < 0) { Loading
drivers/power/supply/qcom/smb-reg.h +2 −0 Original line number Diff line number Diff line Loading @@ -1018,6 +1018,8 @@ enum { #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0) #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1) #define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9) /* CHGR FREQ Peripheral registers */ #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50) Loading