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Commit 27f7ef7c authored by Michael Ira Krufky's avatar Michael Ira Krufky Committed by Mauro Carvalho Chehab
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[media] lgdt3305: add support for fixed tp clock mode 



Add support for controlling TP clock mode for VSB and QAM annex-B/C mode.
Gated clock mode is the default value, and does not support QAM annex-C.
The patch enables setting this control to fixed clock mode.

Signed-off-by: default avatarMichael Ira Krufky <mkrufky@linuxtv.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent bdba90df

drivers/media/dvb-frontends/lgdt3305.c

+3 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) 
	u8 val;

	int ret;

	enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;

	enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;

	enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;



	lg_dbg("edge = %d, valid = %d\n", edge, valid);
@@ -253,6 +254,8 @@ static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state) 


	if (edge)

		val |= 0x08;

	if (mode)

		val |= 0x40;

	if (valid)

		val |= 0x01;

drivers/media/dvb-frontends/lgdt3305.h

+6 −0
Original line number Diff line number Diff line
@@ -37,6 +37,11 @@ enum lgdt3305_tp_clock_edge { 
	LGDT3305_TPCLK_FALLING_EDGE = 1,

};



enum lgdt3305_tp_clock_mode {

	LGDT3305_TPCLK_GATED = 0,

	LGDT3305_TPCLK_FIXED = 1,

};



enum lgdt3305_tp_valid_polarity {

	LGDT3305_TP_VALID_LOW = 0,

	LGDT3305_TP_VALID_HIGH = 1,
@@ -70,6 +75,7 @@ struct lgdt3305_config { 


	enum lgdt3305_mpeg_mode mpeg_mode;

	enum lgdt3305_tp_clock_edge tpclk_edge;

	enum lgdt3305_tp_clock_mode tpclk_mode;

	enum lgdt3305_tp_valid_polarity tpvalid_polarity;

	enum lgdt_demod_chip_type demod_chip;

};