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Commit 273b9465 authored by Paul Walmsley's avatar Paul Walmsley
Browse files

omap_hwmod: share identical omap_hwmod_class, omap_hwmod_class_sysconfig arrays 



To reduce kernel source file data duplication, share struct
omap_hwmod_class and omap_hwmod_class_sysconfig arrays across OMAP2xxx
and 3xxx hwmod data files.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent d826ebfa

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+30 −237
Original line number Diff line number Diff line
@@ -274,24 +274,6 @@ static struct omap_hwmod omap2420_iva_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};



/* Timer Common */

static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_timer_hwmod_class = {

	.name = "timer",

	.sysc = &omap2420_timer_sysc,

	.rev = OMAP_TIMER_IP_VERSION_1,

};



/* timer1 */

static struct omap_hwmod omap2420_timer1_hwmod;
@@ -334,7 +316,7 @@ static struct omap_hwmod omap2420_timer1_hwmod = { 
	},

	.slaves		= omap2420_timer1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer1_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -371,7 +353,7 @@ static struct omap_hwmod omap2420_timer2_hwmod = { 
	},

	.slaves		= omap2420_timer2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer2_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -408,7 +390,7 @@ static struct omap_hwmod omap2420_timer3_hwmod = { 
	},

	.slaves		= omap2420_timer3_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer3_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -445,7 +427,7 @@ static struct omap_hwmod omap2420_timer4_hwmod = { 
	},

	.slaves		= omap2420_timer4_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer4_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -482,7 +464,7 @@ static struct omap_hwmod omap2420_timer5_hwmod = { 
	},

	.slaves		= omap2420_timer5_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer5_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -520,7 +502,7 @@ static struct omap_hwmod omap2420_timer6_hwmod = { 
	},

	.slaves		= omap2420_timer6_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer6_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -557,7 +539,7 @@ static struct omap_hwmod omap2420_timer7_hwmod = { 
	},

	.slaves		= omap2420_timer7_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer7_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -594,7 +576,7 @@ static struct omap_hwmod omap2420_timer8_hwmod = { 
	},

	.slaves		= omap2420_timer8_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer8_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -631,7 +613,7 @@ static struct omap_hwmod omap2420_timer9_hwmod = { 
	},

	.slaves		= omap2420_timer9_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer9_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -668,7 +650,7 @@ static struct omap_hwmod omap2420_timer10_hwmod = { 
	},

	.slaves		= omap2420_timer10_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer10_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -705,7 +687,7 @@ static struct omap_hwmod omap2420_timer11_hwmod = { 
	},

	.slaves		= omap2420_timer11_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer11_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -742,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = { 
	},

	.slaves		= omap2420_timer12_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_timer12_slaves),

	.class		= &omap2420_timer_hwmod_class,

	.class		= &omap2xxx_timer_hwmod_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)

};
@@ -764,27 +746,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/*

 * 'wd_timer' class

 * 32-bit watchdog upward counter that generates a pulse on the reset pin on

 * overflow condition

 */



static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {

	.name		= "wd_timer",

	.sysc		= &omap2420_wd_timer_sysc,

	.pre_shutdown	= &omap2_wd_timer_disable

};



/* wd_timer2 */

static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {

	&omap2420_l4_wkup__wd_timer2,
@@ -792,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 


static struct omap_hwmod omap2420_wd_timer2_hwmod = {

	.name		= "wd_timer2",

	.class		= &omap2420_wd_timer_hwmod_class,

	.class		= &omap2xxx_wd_timer_hwmod_class,

	.main_clk	= "mpu_wdt_fck",

	.prcm		= {

		.omap2 = {
@@ -808,24 +769,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};



/* UART */



static struct omap_hwmod_class_sysconfig uart_sysc = {

	.rev_offs	= 0x50,

	.sysc_offs	= 0x54,

	.syss_offs	= 0x58,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class uart_class = {

	.name = "uart",

	.sysc = &uart_sysc,

};



/* UART1 */



static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
@@ -848,7 +791,7 @@ static struct omap_hwmod omap2420_uart1_hwmod = { 
	},

	.slaves		= omap2420_uart1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_uart1_slaves),

	.class		= &uart_class,

	.class		= &omap2_uart_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -874,7 +817,7 @@ static struct omap_hwmod omap2420_uart2_hwmod = { 
	},

	.slaves		= omap2420_uart2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_uart2_slaves),

	.class		= &uart_class,

	.class		= &omap2_uart_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -900,28 +843,10 @@ static struct omap_hwmod omap2420_uart3_hwmod = { 
	},

	.slaves		= omap2420_uart3_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_uart3_slaves),

	.class		= &uart_class,

	.class		= &omap2_uart_class,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};



/*

 * 'dss' class

 * display sub-system

 */



static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_dss_hwmod_class = {

	.name = "dss",

	.sysc = &omap2420_dss_sysc,

};



/* dss */

/* dss master ports */

static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
@@ -955,7 +880,7 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = { 


static struct omap_hwmod omap2420_dss_core_hwmod = {

	.name		= "dss_core",

	.class		= &omap2420_dss_hwmod_class,

	.class		= &omap2_dss_hwmod_class,

	.main_clk	= "dss1_fck", /* instead of dss_fck */

	.sdma_reqs	= omap2xxx_dss_sdma_chs,

	.prcm		= {
@@ -977,27 +902,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



/*

 * 'dispc' class

 * display controller

 */



static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_dispc_hwmod_class = {

	.name = "dispc",

	.sysc = &omap2420_dispc_sysc,

};



/* l4_core -> dss_dispc */

static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {

	.master		= &omap2420_l4_core_hwmod,
@@ -1020,7 +924,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { 


static struct omap_hwmod omap2420_dss_dispc_hwmod = {

	.name		= "dss_dispc",

	.class		= &omap2420_dispc_hwmod_class,

	.class		= &omap2_dispc_hwmod_class,

	.mpu_irqs	= omap2_dispc_irqs,

	.main_clk	= "dss1_fck",

	.prcm		= {
@@ -1038,26 +942,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



/*

 * 'rfbi' class

 * remote frame buffer interface

 */



static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {

	.name = "rfbi",

	.sysc = &omap2420_rfbi_sysc,

};



/* l4_core -> dss_rfbi */

static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {

	.master		= &omap2420_l4_core_hwmod,
@@ -1080,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { 


static struct omap_hwmod omap2420_dss_rfbi_hwmod = {

	.name		= "dss_rfbi",

	.class		= &omap2420_rfbi_hwmod_class,

	.class		= &omap2_rfbi_hwmod_class,

	.main_clk	= "dss1_fck",

	.prcm		= {

		.omap2 = {
@@ -1095,15 +979,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



/*

 * 'venc' class

 * video encoder

 */



static struct omap_hwmod_class omap2420_venc_hwmod_class = {

	.name = "venc",

};



/* l4_core -> dss_venc */

static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {

	.master		= &omap2420_l4_core_hwmod,
@@ -1127,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { 


static struct omap_hwmod omap2420_dss_venc_hwmod = {

	.name		= "dss_venc",

	.class		= &omap2420_venc_hwmod_class,

	.class		= &omap2_venc_hwmod_class,

	.main_clk	= "dss1_fck",

	.prcm		= {

		.omap2 = {
@@ -1292,27 +1167,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = { 
	.dbck_flag = false,

};



static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |

			   SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



/*

 * 'gpio' class

 * general purpose io module

 */

static struct omap_hwmod_class omap242x_gpio_hwmod_class = {

	.name = "gpio",

	.sysc = &omap242x_gpio_sysc,

	.rev = 0,

};



/* gpio1 */

static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {

	&omap2420_l4_wkup__gpio1,
@@ -1334,7 +1188,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod = { 
	},

	.slaves		= omap2420_gpio1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_gpio1_slaves),

	.class		= &omap242x_gpio_hwmod_class,

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &gpio_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -1360,7 +1214,7 @@ static struct omap_hwmod omap2420_gpio2_hwmod = { 
	},

	.slaves		= omap2420_gpio2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_gpio2_slaves),

	.class		= &omap242x_gpio_hwmod_class,

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &gpio_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -1386,7 +1240,7 @@ static struct omap_hwmod omap2420_gpio3_hwmod = { 
	},

	.slaves		= omap2420_gpio3_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_gpio3_slaves),

	.class		= &omap242x_gpio_hwmod_class,

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &gpio_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -1412,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = { 
	},

	.slaves		= omap2420_gpio4_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_gpio4_slaves),

	.class		= &omap242x_gpio_hwmod_class,

	.class		= &omap2xxx_gpio_hwmod_class,

	.dev_attr	= &gpio_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};



/* system dma */

static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x002c,

	.syss_offs	= 0x0028,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |

			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_dma_hwmod_class = {

	.name = "dma",

	.sysc = &omap2420_dma_sysc,

};



/* dma attributes */

static struct omap_dma_dev_attr dma_dev_attr = {

	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1470,7 +1307,7 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { 


static struct omap_hwmod omap2420_dma_system_hwmod = {

	.name		= "dma",

	.class		= &omap2420_dma_hwmod_class,

	.class		= &omap2xxx_dma_hwmod_class,

	.mpu_irqs	= omap2_dma_system_irqs,

	.main_clk	= "core_l3_ck",

	.slaves		= omap2420_dma_system_slaves,
@@ -1482,27 +1319,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = { 
	.flags		= HWMOD_NO_IDLEST,

};



/*

 * 'mailbox' class

 * mailbox module allowing communication between the on-chip processors

 * using a queued mailbox-interrupt mechanism.

 */



static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {

	.rev_offs	= 0x000,

	.sysc_offs	= 0x010,

	.syss_offs	= 0x014,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {

	.name = "mailbox",

	.sysc = &omap2420_mailbox_sysc,

};



/* mailbox */

static struct omap_hwmod omap2420_mailbox_hwmod;

static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
@@ -1526,7 +1342,7 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { 


static struct omap_hwmod omap2420_mailbox_hwmod = {

	.name		= "mailbox",

	.class		= &omap2420_mailbox_hwmod_class,

	.class		= &omap2xxx_mailbox_hwmod_class,

	.mpu_irqs	= omap2420_mailbox_irqs,

	.main_clk	= "mailboxes_ick",

	.prcm		= {
@@ -1543,29 +1359,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};



/*

 * 'mcspi' class

 * multichannel serial port interface (mcspi) / master/slave synchronous serial

 * bus

 */



static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |

				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap2420_mcspi_class = {

	.name = "mcspi",

	.sysc = &omap2420_mcspi_sysc,

	.rev = OMAP2_MCSPI_REV,

};



/* mcspi1 */

static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {

	&omap2420_l4_core__mcspi1,
@@ -1591,7 +1384,7 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = { 
	},

	.slaves		= omap2420_mcspi1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi1_slaves),

	.class		= &omap2420_mcspi_class,

	.class		= &omap2xxx_mcspi_class,

	.dev_attr	= &omap_mcspi1_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};
@@ -1621,7 +1414,7 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = { 
	},

	.slaves		= omap2420_mcspi2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi2_slaves),

	.class		= &omap2420_mcspi_class,

	.class		= &omap2xxx_mcspi_class,

	.dev_attr	= &omap_mcspi2_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+33 −240

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

+158 −70
Original line number Diff line number Diff line
@@ -16,6 +16,164 @@ 


#include "omap_hwmod_common_data.h"



/* UART */



static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {

	.rev_offs	= 0x50,

	.sysc_offs	= 0x54,

	.syss_offs	= 0x58,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_uart_class = {

	.name	= "uart",

	.sysc	= &omap2_uart_sysc,

};



/*

 * 'dss' class

 * display sub-system

 */



static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_dss_hwmod_class = {

	.name	= "dss",

	.sysc	= &omap2_dss_sysc,

};



/*

 * 'dispc' class

 * display controller

 */



static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |

			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_dispc_hwmod_class = {

	.name	= "dispc",

	.sysc	= &omap2_dispc_sysc,

};



/*

 * 'rfbi' class

 * remote frame buffer interface

 */



static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2_rfbi_hwmod_class = {

	.name	= "rfbi",

	.sysc	= &omap2_rfbi_sysc,

};



/*

 * 'venc' class

 * video encoder

 */



struct omap_hwmod_class omap2_venc_hwmod_class = {

	.name = "venc",

};





/* Common DMA request line data */

struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {

	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */

	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */

	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */

	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */

	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */

	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */

	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */

	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {

	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */

	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */

	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */

	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 32 },

	{ .name = "tx", .dma_req = 31 },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 34 },

	{ .name = "tx", .dma_req = 33 },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 18 },

	{ .name = "tx", .dma_req = 17 },

	{ .dma_req = -1 }

};



/* Other IP block data */





/*

 * omap_hwmod class data
@@ -162,73 +320,3 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = { 
	{ .irq = -1 }

};

/* Common DMA request line data */

struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {

	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },

	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {

	{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */

	{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */

	{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */

	{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */

	{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */

	{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */

	{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */

	{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {

	{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */

	{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */

	{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */

	{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 32 },

	{ .name = "tx", .dma_req = 31 },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 34 },

	{ .name = "tx", .dma_req = 33 },

	{ .dma_req = -1 }

};



struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {

	{ .name = "rx", .dma_req = 18 },

	{ .name = "tx", .dma_req = 17 },

	{ .dma_req = -1 }

};

arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

+123 −0
Original line number Diff line number Diff line
@@ -11,10 +11,13 @@ 
#include <plat/omap_hwmod.h>

#include <plat/serial.h>

#include <plat/dma.h>

#include <plat/dmtimer.h>

#include <plat/mcspi.h>



#include <mach/irqs.h>



#include "omap_hwmod_common_data.h"

#include "wd_timer.h"



struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {

	{ .irq = 48, },
@@ -25,3 +28,123 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 
	{ .name = "dispc", .dma_req = 5 },

	{ .dma_req = -1 }

};

/* OMAP2xxx Timer Common */

static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_timer_hwmod_class = {

	.name	= "timer",

	.sysc	= &omap2xxx_timer_sysc,

	.rev	= OMAP_TIMER_IP_VERSION_1,

};



/*

 * 'wd_timer' class

 * 32-bit watchdog upward counter that generates a pulse on the reset pin on

 * overflow condition

 */



static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {

	.name		= "wd_timer",

	.sysc		= &omap2xxx_wd_timer_sysc,

	.pre_shutdown	= &omap2_wd_timer_disable

};



/*

 * 'gpio' class

 * general purpose io module

 */

static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |

			   SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {

	.name = "gpio",

	.sysc = &omap2xxx_gpio_sysc,

	.rev = 0,

};



/* system dma */

static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x002c,

	.syss_offs	= 0x0028,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |

			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |

			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_dma_hwmod_class = {

	.name	= "dma",

	.sysc	= &omap2xxx_dma_sysc,

};



/*

 * 'mailbox' class

 * mailbox module allowing communication between the on-chip processors

 * using a queued mailbox-interrupt mechanism.

 */



static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {

	.rev_offs	= 0x000,

	.sysc_offs	= 0x010,

	.syss_offs	= 0x014,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {

	.name	= "mailbox",

	.sysc	= &omap2xxx_mailbox_sysc,

};



/*

 * 'mcspi' class

 * multichannel serial port interface (mcspi) / master/slave synchronous serial

 * bus

 */



static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {

	.rev_offs	= 0x0000,

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0014,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |

				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



struct omap_hwmod_class omap2xxx_mcspi_class = {

	.name	= "mcspi",

	.sysc	= &omap2xxx_mcspi_sysc,

	.rev	= OMAP2_MCSPI_REV,

};

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

+9 −96

File changed.

Preview size limit exceeded, changes collapsed.