Loading drivers/char/diag/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -37,7 +37,7 @@ config DIAGFWD_BRIDGE_CODE config DIAG_OVER_PCIE bool "Enable Diag traffic to go over PCIE" depends on DIAG_CHAR depends on MSM_MHI depends on MSM_MHI_DEV help Diag over PCIE enables sending diag traffic over PCIE endpoint when pcie is available. Diag PCIE channels should be configured Loading drivers/char/diag/diag_mux.c +1 −1 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ int diag_pcie_register_ops(int proc, int ctx, struct diag_mux_ops *ops) pcie_logger.ops[proc] = ops; err = diag_pcie_register(proc, ctx, ops); if (err) { driver->transport_set == DIAG_ROUTE_TO_USB; driver->transport_set = DIAG_ROUTE_TO_USB; diag_mux->logger = &usb_logger; diag_mux->mode = DIAG_USB_MODE; usb_logger.ops[proc] = ops; Loading drivers/char/diag/diag_pcie.c +13 −14 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ struct diag_pcie_info diag_pcie[NUM_DIAG_PCIE_DEV] = { { .id = DIAG_PCIE_LOCAL, .name = DIAG_LEGACY, .enabled = 0, .enabled = {0}, .mempool = POOL_TYPE_MUX_APPS, .ops = NULL, .wq = NULL, Loading Loading @@ -171,6 +171,8 @@ void diag_pcie_write_complete_cb(void *req) diag_ws_on_copy_complete(DIAG_WS_MUX); spin_unlock_irqrestore(&ch->write_lock, flags); diagmem_free(driver, req, ch->mempool); kfree(ctxt); ctxt = NULL; return; } DIAG_LOG(DIAG_DEBUG_MUX, "full write_done, ctxt: %pK\n", Loading Loading @@ -281,19 +283,19 @@ static int diag_pcie_write_ext(struct diag_pcie_info *pcie_info, bytes_to_write = mhi_dev_write_channel(req); diag_ws_on_copy(DIAG_WS_MUX); if (bytes_to_write != write_len) { pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d\n", pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d, write_len: %d\n", __func__, pcie_info->name, bytes_to_write); bytes_to_write, write_len); DIAG_LOG(DIAG_DEBUG_MUX, "ERR! unable to write to pcie, err: %d\n", bytes_to_write); "ERR! unable to write to pcie, err: %d, write_len: %d\n", bytes_to_write, write_len); diag_ws_on_copy_fail(DIAG_WS_MUX); spin_lock_irqsave(&pcie_info->write_lock, flags); diag_pcie_buf_tbl_remove(pcie_info, buf); kfree(req->context); diagmem_free(driver, req, pcie_info->mempool); spin_unlock_irqrestore(&pcie_info->write_lock, flags); return bytes_to_write; return -EINVAL; } offset += write_len; bytes_remaining -= write_len; Loading Loading @@ -365,17 +367,18 @@ int diag_pcie_write(int id, unsigned char *buf, int len, int ctxt) bytes_to_write = mhi_dev_write_channel(req); diag_ws_on_copy(DIAG_WS_MUX); if (bytes_to_write != len) { pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d\n", __func__, pcie_info->name, bytes_to_write); pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d len: %d\n", __func__, pcie_info->name, bytes_to_write, len); diag_ws_on_copy_fail(DIAG_WS_MUX); DIAG_LOG(DIAG_DEBUG_MUX, "ERR! unable to write to pcie, err: %d\n", bytes_to_write); "ERR! unable to write to pcie, err: %d len: %d\n", bytes_to_write, len); spin_lock_irqsave(&pcie_info->write_lock, flags); diag_pcie_buf_tbl_remove(pcie_info, buf); spin_unlock_irqrestore(&pcie_info->write_lock, flags); kfree(req->context); diagmem_free(driver, req, pcie_info->mempool); return -EINVAL; } DIAG_LOG(DIAG_DEBUG_MUX, "wrote packet to pcie chan:%d, len:%d", pcie_info->out_chan, len); Loading Loading @@ -475,10 +478,6 @@ static int diag_register_pcie_channels(struct diag_pcie_info *pcie_info) static void diag_pcie_connect(struct diag_pcie_info *ch) { int err = 0; int num_write = 0; int num_read = 1; /* Only one read buffer for any pcie channel */ if (!ch || !atomic_read(&ch->enabled)) return; Loading Loading
drivers/char/diag/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -37,7 +37,7 @@ config DIAGFWD_BRIDGE_CODE config DIAG_OVER_PCIE bool "Enable Diag traffic to go over PCIE" depends on DIAG_CHAR depends on MSM_MHI depends on MSM_MHI_DEV help Diag over PCIE enables sending diag traffic over PCIE endpoint when pcie is available. Diag PCIE channels should be configured Loading
drivers/char/diag/diag_mux.c +1 −1 Original line number Diff line number Diff line Loading @@ -127,7 +127,7 @@ int diag_pcie_register_ops(int proc, int ctx, struct diag_mux_ops *ops) pcie_logger.ops[proc] = ops; err = diag_pcie_register(proc, ctx, ops); if (err) { driver->transport_set == DIAG_ROUTE_TO_USB; driver->transport_set = DIAG_ROUTE_TO_USB; diag_mux->logger = &usb_logger; diag_mux->mode = DIAG_USB_MODE; usb_logger.ops[proc] = ops; Loading
drivers/char/diag/diag_pcie.c +13 −14 Original line number Diff line number Diff line Loading @@ -33,7 +33,7 @@ struct diag_pcie_info diag_pcie[NUM_DIAG_PCIE_DEV] = { { .id = DIAG_PCIE_LOCAL, .name = DIAG_LEGACY, .enabled = 0, .enabled = {0}, .mempool = POOL_TYPE_MUX_APPS, .ops = NULL, .wq = NULL, Loading Loading @@ -171,6 +171,8 @@ void diag_pcie_write_complete_cb(void *req) diag_ws_on_copy_complete(DIAG_WS_MUX); spin_unlock_irqrestore(&ch->write_lock, flags); diagmem_free(driver, req, ch->mempool); kfree(ctxt); ctxt = NULL; return; } DIAG_LOG(DIAG_DEBUG_MUX, "full write_done, ctxt: %pK\n", Loading Loading @@ -281,19 +283,19 @@ static int diag_pcie_write_ext(struct diag_pcie_info *pcie_info, bytes_to_write = mhi_dev_write_channel(req); diag_ws_on_copy(DIAG_WS_MUX); if (bytes_to_write != write_len) { pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d\n", pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d, write_len: %d\n", __func__, pcie_info->name, bytes_to_write); bytes_to_write, write_len); DIAG_LOG(DIAG_DEBUG_MUX, "ERR! unable to write to pcie, err: %d\n", bytes_to_write); "ERR! unable to write to pcie, err: %d, write_len: %d\n", bytes_to_write, write_len); diag_ws_on_copy_fail(DIAG_WS_MUX); spin_lock_irqsave(&pcie_info->write_lock, flags); diag_pcie_buf_tbl_remove(pcie_info, buf); kfree(req->context); diagmem_free(driver, req, pcie_info->mempool); spin_unlock_irqrestore(&pcie_info->write_lock, flags); return bytes_to_write; return -EINVAL; } offset += write_len; bytes_remaining -= write_len; Loading Loading @@ -365,17 +367,18 @@ int diag_pcie_write(int id, unsigned char *buf, int len, int ctxt) bytes_to_write = mhi_dev_write_channel(req); diag_ws_on_copy(DIAG_WS_MUX); if (bytes_to_write != len) { pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d\n", __func__, pcie_info->name, bytes_to_write); pr_err_ratelimited("diag: In %s, error writing to pcie channel %s, err: %d len: %d\n", __func__, pcie_info->name, bytes_to_write, len); diag_ws_on_copy_fail(DIAG_WS_MUX); DIAG_LOG(DIAG_DEBUG_MUX, "ERR! unable to write to pcie, err: %d\n", bytes_to_write); "ERR! unable to write to pcie, err: %d len: %d\n", bytes_to_write, len); spin_lock_irqsave(&pcie_info->write_lock, flags); diag_pcie_buf_tbl_remove(pcie_info, buf); spin_unlock_irqrestore(&pcie_info->write_lock, flags); kfree(req->context); diagmem_free(driver, req, pcie_info->mempool); return -EINVAL; } DIAG_LOG(DIAG_DEBUG_MUX, "wrote packet to pcie chan:%d, len:%d", pcie_info->out_chan, len); Loading Loading @@ -475,10 +478,6 @@ static int diag_register_pcie_channels(struct diag_pcie_info *pcie_info) static void diag_pcie_connect(struct diag_pcie_info *ch) { int err = 0; int num_write = 0; int num_read = 1; /* Only one read buffer for any pcie channel */ if (!ch || !atomic_read(&ch->enabled)) return; Loading