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Commit 26c19760 authored by Vasanthakumar Thiagarajan's avatar Vasanthakumar Thiagarajan Committed by Kalle Valo
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ath10k: define an enum to enable cycle counter wraparound logic 



QCA988X hw implements a different cycle counter wraparound
behaviour when compared to QCA4019. To properly handle different
wraparound logic for these chipsets replace already available
bool hw_params member, has_shifted_cc_wraparound, with an
enum which could be extended to handle different wraparound
behaviour. This patch keeps the existing logic functionally
same and a prepares cycle counter wraparound handling to
extend for other chips.

Signed-off-by: default avatarVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
[kvalo@qca.qualcomm.com: change also QCA9887 wrap type]
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent 5269c659

drivers/net/wireless/ath/ath10k/core.c

+3 −3
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.name = "qca988x hw2.0",

		.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,

		.uart_pin = 7,

		.has_shifted_cc_wraparound = true,

		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.max_probe_resp_desc_thres = 0,
@@ -75,7 +75,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.name = "qca9887 hw1.0",

		.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,

		.uart_pin = 7,

		.has_shifted_cc_wraparound = true,

		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,

		.otp_exe_param = 0,

		.channel_counters_freq_hz = 88000,

		.max_probe_resp_desc_thres = 0,
@@ -246,7 +246,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.name = "qca4019 hw1.0",

		.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,

		.uart_pin = 7,

		.has_shifted_cc_wraparound = true,

		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,

		.otp_exe_param = 0x0010000,

		.continuous_frag_desc = true,

		.cck_rate_map_rev2 = true,

drivers/net/wireless/ath/ath10k/core.h

+3 −5
Original line number Diff line number Diff line
@@ -713,12 +713,10 @@ struct ath10k { 
		int uart_pin;

		u32 otp_exe_param;



		/* This is true if given HW chip has a quirky Cycle Counter

		 * wraparound which resets to 0x7fffffff instead of 0. All

		 * other CC related counters (e.g. Rx Clear Count) are divided

		 * by 2 so they never wraparound themselves.

		/* Type of hw cycle counter wraparound logic, for more info

		 * refer enum ath10k_hw_cc_wraparound_type.

		 */

		bool has_shifted_cc_wraparound;

		enum ath10k_hw_cc_wraparound_type cc_wraparound_type;



		/* Some of chip expects fragment descriptor to be continuous

		 * memory for any TX operation. Set continuous_frag_desc flag

drivers/net/wireless/ath/ath10k/hw.c

+3 −1
Original line number Diff line number Diff line
@@ -179,11 +179,13 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, 
				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)

{

	u32 cc_fix = 0;

	enum ath10k_hw_cc_wraparound_type wraparound_type;



	survey->filled |= SURVEY_INFO_TIME |

			  SURVEY_INFO_TIME_BUSY;



	if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {

	wraparound_type = ar->hw_params.cc_wraparound_type;

	if (wraparound_type == ATH10K_HW_CC_WRAP_SHIFTED_ALL && cc < cc_prev) {

		cc_fix = 0x7fffffff;

		survey->filled &= ~SURVEY_INFO_TIME_BUSY;

	}

drivers/net/wireless/ath/ath10k/hw.h

+11 −0
Original line number Diff line number Diff line
@@ -351,6 +351,17 @@ enum ath10k_hw_4addr_pad { 
	ATH10K_HW_4ADDR_PAD_BEFORE,

};



enum ath10k_hw_cc_wraparound_type {

	ATH10K_HW_CC_WRAP_DISABLED = 0,



	/* This type is when the HW chip has a quirky Cycle Counter

	 * wraparound which resets to 0x7fffffff instead of 0. All

	 * other CC related counters (e.g. Rx Clear Count) are divided

	 * by 2 so they never wraparound themselves.

	 */

	ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,

};



/* Target specific defines for MAIN firmware */

#define TARGET_NUM_VDEVS			8

#define TARGET_NUM_PEER_AST			2