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Commit 26beaee9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-etnaviv-fixes' of git://git.pengutronix.de/lst/linux into drm-fixes 

2 more patches to stabilize the new MMUv2 support.

* 'drm-etnaviv-fixes' of git://git.pengutronix.de/lst/linux:
  drm/etnaviv: block 64K of address space behind each cmdstream
  drm/etnaviv: ensure write caches are flushed at end of user cmdstream
parents 96ebf7cb 8814d2dc

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

+19 −5
Original line number Diff line number Diff line
@@ -329,20 +329,34 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event, 
	/*

	 * Append a LINK to the submitted command buffer to return to

	 * the ring buffer.  return_target is the ring target address.

	 * We need three dwords: event, wait, link.

	 * We need at most 7 dwords in the return target: 2 cache flush +

	 * 2 semaphore stall + 1 event + 1 wait + 1 link.

	 */

	return_dwords = 3;

	return_dwords = 7;

	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);

	CMD_LINK(cmdbuf, return_dwords, return_target);



	/*

	 * Append event, wait and link pointing back to the wait

	 * command to the ring buffer.

	 * Append a cache flush, stall, event, wait and link pointing back to

	 * the wait command to the ring buffer.

	 */

	if (gpu->exec_state == ETNA_PIPE_2D) {

		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,

				       VIVS_GL_FLUSH_CACHE_PE2D);

	} else {

		CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE,

				       VIVS_GL_FLUSH_CACHE_DEPTH |

				       VIVS_GL_FLUSH_CACHE_COLOR);

		CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE,

				       VIVS_TS_FLUSH_CACHE_FLUSH);

	}

	CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);

	CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);

	CMD_LOAD_STATE(buffer, VIVS_GL_EVENT, VIVS_GL_EVENT_EVENT_ID(event) |

		       VIVS_GL_EVENT_FROM_PE);

	CMD_WAIT(buffer);

	CMD_LINK(buffer, 2, return_target + 8);

	CMD_LINK(buffer, 2, etnaviv_iommu_get_cmdbuf_va(gpu, buffer) +

			    buffer->user_size - 4);



	if (drm_debug & DRM_UT_DRIVER)

		pr_info("stream link to 0x%08x @ 0x%08x %p\n",

drivers/gpu/drm/etnaviv/etnaviv_mmu.c

+2 −1
Original line number Diff line number Diff line
@@ -330,7 +330,8 @@ u32 etnaviv_iommu_get_cmdbuf_va(struct etnaviv_gpu *gpu, 
			return (u32)buf->vram_node.start;



		mutex_lock(&mmu->lock);

		ret = etnaviv_iommu_find_iova(mmu, &buf->vram_node, buf->size);

		ret = etnaviv_iommu_find_iova(mmu, &buf->vram_node,

					      buf->size + SZ_64K);

		if (ret < 0) {

			mutex_unlock(&mmu->lock);

			return 0;