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Commit 26955c07 authored by Lee Jones's avatar Lee Jones Committed by Linus Walleij
Browse files

dmaengine: ste_dma40: Amalgamate DMA source and destination channel numbers 



Devices which utilise DMA use the same device numbers for transmitting
and receiving. In this patch we encode the source and destination
information into one single attribute. We can subsequently exploit the
direction attribute to see which of the transfer directions are being
described. This also lessens the burden on platform data.

Cc: Dan Williams <djbw@fb.com>
Cc: Per Forlin <per.forlin@stericsson.com>
Cc: Rabin Vincent <rabin@rab.in>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 4f8fc46c

arch/arm/mach-ux500/board-mop500-audio.c

+6 −12
Original line number Diff line number Diff line
@@ -23,8 +23,7 @@ static struct stedma40_chan_cfg msp0_dma_rx = { 
	.high_priority = true,

	.dir = STEDMA40_PERIPH_TO_MEM,



	.src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,



	.src_info.psize = STEDMA40_PSIZE_LOG_4,

	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -36,8 +35,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = { 
	.high_priority = true,

	.dir = STEDMA40_MEM_TO_PERIPH,



	.src_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,

	.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,



	.src_info.psize = STEDMA40_PSIZE_LOG_4,

	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -55,8 +53,7 @@ static struct stedma40_chan_cfg msp1_dma_rx = { 
	.high_priority = true,

	.dir = STEDMA40_PERIPH_TO_MEM,



	.src_dev_type = DB8500_DMA_DEV30_MSP3_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV30_MSP3,



	.src_info.psize = STEDMA40_PSIZE_LOG_4,

	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -68,8 +65,7 @@ static struct stedma40_chan_cfg msp1_dma_tx = { 
	.high_priority = true,

	.dir = STEDMA40_MEM_TO_PERIPH,



	.src_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,

	.dev_type = DB8500_DMA_DEV30_MSP1,



	.src_info.psize = STEDMA40_PSIZE_LOG_4,

	.dst_info.psize = STEDMA40_PSIZE_LOG_4,
@@ -87,8 +83,7 @@ static struct stedma40_chan_cfg msp2_dma_rx = { 
	.high_priority = true,

	.dir = STEDMA40_PERIPH_TO_MEM,



	.src_dev_type = DB8500_DMA_DEV14_MSP2_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV14_MSP2,



	/* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */

	.src_info.psize = STEDMA40_PSIZE_LOG_1,
@@ -101,8 +96,7 @@ static struct stedma40_chan_cfg msp2_dma_tx = { 
	.high_priority = true,

	.dir = STEDMA40_MEM_TO_PERIPH,



	.src_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,

	.dev_type = DB8500_DMA_DEV14_MSP2,



	.src_info.psize = STEDMA40_PSIZE_LOG_4,

	.dst_info.psize = STEDMA40_PSIZE_LOG_4,

arch/arm/mach-ux500/board-mop500-sdi.c

+8 −16
Original line number Diff line number Diff line
@@ -35,8 +35,7 @@ 
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV29_SD_MM0,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -44,8 +43,7 @@ struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = { 
static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,

	.dev_type = DB8500_DMA_DEV29_SD_MM0,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -88,8 +86,7 @@ void mop500_sdi_tc35892_init(struct device *parent) 
static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV32_SD_MM1,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -97,8 +94,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_rx = { 
static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,

	.dev_type = DB8500_DMA_DEV32_SD_MM1,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -125,8 +121,7 @@ struct mmci_platform_data mop500_sdi1_data = { 
struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type =  DB8500_DMA_DEV28_SD_MM2,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -134,8 +129,7 @@ struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = { 
static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,

	.dev_type = DB8500_DMA_DEV28_SD_MM2,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -163,8 +157,7 @@ struct mmci_platform_data mop500_sdi2_data = { 
struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type =  DB8500_DMA_DEV42_SD_MM4,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};
@@ -172,8 +165,7 @@ struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = { 
static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,

	.dev_type = DB8500_DMA_DEV42_SD_MM4,

	.src_info.data_width = STEDMA40_WORD_WIDTH,

	.dst_info.data_width = STEDMA40_WORD_WIDTH,

};

arch/arm/mach-ux500/board-mop500.c

+11 −22
Original line number Diff line number Diff line
@@ -425,8 +425,7 @@ void mop500_snowball_ethernet_clock_enable(void) 
static struct cryp_platform_data u8500_cryp1_platform_data = {

		.mem_to_engine = {

				.dir = STEDMA40_MEM_TO_PERIPH,

				.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

				.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,

				.dev_type = DB8500_DMA_DEV48_CAC1,

				.src_info.data_width = STEDMA40_WORD_WIDTH,

				.dst_info.data_width = STEDMA40_WORD_WIDTH,

				.mode = STEDMA40_MODE_LOGICAL,
@@ -435,8 +434,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = { 
		},

		.engine_to_mem = {

				.dir = STEDMA40_PERIPH_TO_MEM,

				.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,

				.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

				.dev_type = DB8500_DMA_DEV48_CAC1,

				.src_info.data_width = STEDMA40_WORD_WIDTH,

				.dst_info.data_width = STEDMA40_WORD_WIDTH,

				.mode = STEDMA40_MODE_LOGICAL,
@@ -447,8 +445,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = { 


static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {

		.dir = STEDMA40_MEM_TO_PERIPH,

		.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

		.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,

		.dev_type = DB8500_DMA_DEV50_HAC1_TX,

		.src_info.data_width = STEDMA40_WORD_WIDTH,

		.dst_info.data_width = STEDMA40_WORD_WIDTH,

		.mode = STEDMA40_MODE_LOGICAL,
@@ -471,8 +468,7 @@ static struct platform_device *mop500_platform_devs[] __initdata = { 
static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV8_SSP0,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -480,8 +476,7 @@ static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { 
static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,

	.dev_type = DB8500_DMA_DEV8_SSP0,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -512,8 +507,7 @@ static void __init mop500_spi_init(struct device *parent) 
static struct stedma40_chan_cfg uart0_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV13_UART0_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV13_UART0,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -521,8 +515,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_rx = { 
static struct stedma40_chan_cfg uart0_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV13_UART0_TX,

	.dev_type = DB8500_DMA_DEV13_UART0,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -530,8 +523,7 @@ static struct stedma40_chan_cfg uart0_dma_cfg_tx = { 
static struct stedma40_chan_cfg uart1_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV12_UART1_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV12_UART1,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -539,8 +531,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_rx = { 
static struct stedma40_chan_cfg uart1_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV12_UART1_TX,

	.dev_type = DB8500_DMA_DEV12_UART1,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -548,8 +539,7 @@ static struct stedma40_chan_cfg uart1_dma_cfg_tx = { 
static struct stedma40_chan_cfg uart2_dma_cfg_rx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_PERIPH_TO_MEM,

	.src_dev_type =  DB8500_DMA_DEV11_UART2_RX,

	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,

	.dev_type = DB8500_DMA_DEV11_UART2,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};
@@ -557,8 +547,7 @@ static struct stedma40_chan_cfg uart2_dma_cfg_rx = { 
static struct stedma40_chan_cfg uart2_dma_cfg_tx = {

	.mode = STEDMA40_MODE_LOGICAL,

	.dir = STEDMA40_MEM_TO_PERIPH,

	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,

	.dst_dev_type = DB8500_DMA_DEV11_UART2_TX,

	.dev_type = DB8500_DMA_DEV11_UART2,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

};

arch/arm/mach-ux500/cpu-db8500.c

+16 −16
Original line number Diff line number Diff line
@@ -163,25 +163,25 @@ static void __init db8500_add_gpios(struct device *parent) 
}



static int usb_db8500_rx_dma_cfg[] = {

	DB8500_DMA_DEV38_USB_OTG_IEP_1_9,

	DB8500_DMA_DEV37_USB_OTG_IEP_2_10,

	DB8500_DMA_DEV36_USB_OTG_IEP_3_11,

	DB8500_DMA_DEV19_USB_OTG_IEP_4_12,

	DB8500_DMA_DEV18_USB_OTG_IEP_5_13,

	DB8500_DMA_DEV17_USB_OTG_IEP_6_14,

	DB8500_DMA_DEV16_USB_OTG_IEP_7_15,

	DB8500_DMA_DEV39_USB_OTG_IEP_8

	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,

	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,

	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,

	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,

	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,

	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,

	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,

	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8

};



static int usb_db8500_tx_dma_cfg[] = {

	DB8500_DMA_DEV38_USB_OTG_OEP_1_9,

	DB8500_DMA_DEV37_USB_OTG_OEP_2_10,

	DB8500_DMA_DEV36_USB_OTG_OEP_3_11,

	DB8500_DMA_DEV19_USB_OTG_OEP_4_12,

	DB8500_DMA_DEV18_USB_OTG_OEP_5_13,

	DB8500_DMA_DEV17_USB_OTG_OEP_6_14,

	DB8500_DMA_DEV16_USB_OTG_OEP_7_15,

	DB8500_DMA_DEV39_USB_OTG_OEP_8

	DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,

	DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,

	DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,

	DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,

	DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,

	DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,

	DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,

	DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8

};



static const char *db8500_read_soc_id(void)

arch/arm/mach-ux500/devices-db8500.c

+60 −60
Original line number Diff line number Diff line
@@ -50,74 +50,74 @@ static struct resource dma40_resources[] = { 
 */

static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {

	/* MUSB - these will be runtime-reconfigured */

	[DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,

	[DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,

	[DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,

	[DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,

	[DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,

	[DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,

	[DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,

	[DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,

	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,

	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,

	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,

	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,

	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,

	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,

	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,

	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,

	/* PrimeCells - run-time configured */

	[DB8500_DMA_DEV0_SPI0_TX] = -1,

	[DB8500_DMA_DEV1_SD_MMC0_TX] = -1,

	[DB8500_DMA_DEV2_SD_MMC1_TX] = -1,

	[DB8500_DMA_DEV3_SD_MMC2_TX] = -1,

	[DB8500_DMA_DEV8_SSP0_TX] = -1,

	[DB8500_DMA_DEV9_SSP1_TX] = -1,

	[DB8500_DMA_DEV11_UART2_TX] = -1,

	[DB8500_DMA_DEV12_UART1_TX] = -1,

	[DB8500_DMA_DEV13_UART0_TX] = -1,

	[DB8500_DMA_DEV28_SD_MM2_TX] = -1,

	[DB8500_DMA_DEV29_SD_MM0_TX] = -1,

	[DB8500_DMA_DEV32_SD_MM1_TX] = -1,

	[DB8500_DMA_DEV33_SPI2_TX] = -1,

	[DB8500_DMA_DEV35_SPI1_TX] = -1,

	[DB8500_DMA_DEV40_SPI3_TX] = -1,

	[DB8500_DMA_DEV41_SD_MM3_TX] = -1,

	[DB8500_DMA_DEV42_SD_MM4_TX] = -1,

	[DB8500_DMA_DEV43_SD_MM5_TX] = -1,

	[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,

	[DB8500_DMA_DEV0_SPI0] = -1,

	[DB8500_DMA_DEV1_SD_MMC0] = -1,

	[DB8500_DMA_DEV2_SD_MMC1] = -1,

	[DB8500_DMA_DEV3_SD_MMC2] = -1,

	[DB8500_DMA_DEV8_SSP0] = -1,

	[DB8500_DMA_DEV9_SSP1] = -1,

	[DB8500_DMA_DEV11_UART2] = -1,

	[DB8500_DMA_DEV12_UART1] = -1,

	[DB8500_DMA_DEV13_UART0] = -1,

	[DB8500_DMA_DEV28_SD_MM2] = -1,

	[DB8500_DMA_DEV29_SD_MM0] = -1,

	[DB8500_DMA_DEV32_SD_MM1] = -1,

	[DB8500_DMA_DEV33_SPI2] = -1,

	[DB8500_DMA_DEV35_SPI1] = -1,

	[DB8500_DMA_DEV40_SPI3] = -1,

	[DB8500_DMA_DEV41_SD_MM3] = -1,

	[DB8500_DMA_DEV42_SD_MM4] = -1,

	[DB8500_DMA_DEV43_SD_MM5] = -1,

	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,

	[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,

};



/* Mapping between source event lines and physical device address */

static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {

	/* MUSB - these will be runtime-reconfigured */

	[DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,

	[DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,

	[DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,

	[DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,

	[DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,

	[DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,

	[DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,

	[DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,

	[DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,

	[DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,

	[DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,

	[DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,

	[DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,

	[DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,

	[DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,

	[DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,

	/* PrimeCells */

	[DB8500_DMA_DEV0_SPI0_RX] = -1,

	[DB8500_DMA_DEV1_SD_MMC0_RX] = -1,

	[DB8500_DMA_DEV2_SD_MMC1_RX] = -1,

	[DB8500_DMA_DEV3_SD_MMC2_RX] = -1,

	[DB8500_DMA_DEV8_SSP0_RX] = -1,

	[DB8500_DMA_DEV9_SSP1_RX] = -1,

	[DB8500_DMA_DEV11_UART2_RX] = -1,

	[DB8500_DMA_DEV12_UART1_RX] = -1,

	[DB8500_DMA_DEV13_UART0_RX] = -1,

	[DB8500_DMA_DEV28_SD_MM2_RX] = -1,

	[DB8500_DMA_DEV29_SD_MM0_RX] = -1,

	[DB8500_DMA_DEV32_SD_MM1_RX] = -1,

	[DB8500_DMA_DEV33_SPI2_RX] = -1,

	[DB8500_DMA_DEV35_SPI1_RX] = -1,

	[DB8500_DMA_DEV40_SPI3_RX] = -1,

	[DB8500_DMA_DEV41_SD_MM3_RX] = -1,

	[DB8500_DMA_DEV42_SD_MM4_RX] = -1,

	[DB8500_DMA_DEV43_SD_MM5_RX] = -1,

	[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,

	[DB8500_DMA_DEV0_SPI0] = -1,

	[DB8500_DMA_DEV1_SD_MMC0] = -1,

	[DB8500_DMA_DEV2_SD_MMC1] = -1,

	[DB8500_DMA_DEV3_SD_MMC2] = -1,

	[DB8500_DMA_DEV8_SSP0] = -1,

	[DB8500_DMA_DEV9_SSP1] = -1,

	[DB8500_DMA_DEV11_UART2] = -1,

	[DB8500_DMA_DEV12_UART1] = -1,

	[DB8500_DMA_DEV13_UART0] = -1,

	[DB8500_DMA_DEV28_SD_MM2] = -1,

	[DB8500_DMA_DEV29_SD_MM0] = -1,

	[DB8500_DMA_DEV32_SD_MM1] = -1,

	[DB8500_DMA_DEV33_SPI2] = -1,

	[DB8500_DMA_DEV35_SPI1] = -1,

	[DB8500_DMA_DEV40_SPI3] = -1,

	[DB8500_DMA_DEV41_SD_MM3] = -1,

	[DB8500_DMA_DEV42_SD_MM4] = -1,

	[DB8500_DMA_DEV43_SD_MM5] = -1,

	[DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,

	[DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,

};



static struct stedma40_platform_data dma40_plat_data = {