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Commit 25e4ce4c authored by Narender Ankam's avatar Narender Ankam
Browse files

drm/msm/dp: clear CP_IRQ bit during hdcp2p2 authentication 



Though CP_IRQ bit is being cleared during HDCP1.4 authentication,
it is not being cleared during HDCP2.2 authentication.
This change now clears CP_IRQ bit after processing cp_irq handler
during HDCP2.2 authentication.

Change-Id: Ice165322d4fc5bfa5c43d62e33d2eab5452d9a29
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
parent 7d7c5b26

drivers/gpu/drm/msm/dp/dp_hdcp2p2.c

+17 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ 


#define DP_INTR_STATUS2				(0x00000024)

#define DP_INTR_STATUS3				(0x00000028)



#define DP_DPCD_CP_IRQ                          (0x201)



#define dp_read(offset) readl_relaxed((offset))

#define dp_write(offset, data) writel_relaxed((data), (offset))

#define DP_HDCP_RXCAPS_LENGTH 3
@@ -393,6 +396,7 @@ static int dp_hdcp2p2_aux_write_message(struct dp_hdcp2p2_ctrl *ctrl, 
		if (bytes_written != write_size) {

			pr_err("fail: offset(0x%x), size(0x%x), rc(0x%x)\n",

					offset, write_size, bytes_written);

			rc = bytes_written;

			break;

		}
@@ -675,6 +679,18 @@ static int dp_hdcp2p2_read_rx_status(struct dp_hdcp2p2_ctrl *ctrl, 
	return rc;

}



static void dp_hdcp2p2_clear_cp_irq(struct dp_hdcp2p2_ctrl *ctrl)

{

	int rc = 0;

	u8 buf = BIT(2);

	u32 const default_timeout_us = 500;



	rc = dp_hdcp2p2_aux_write_message(ctrl, &buf, 1,

			DP_DPCD_CP_IRQ, default_timeout_us);

	if (rc)

		pr_err("error clearing irq_vector\n");

}



static int dp_hdcp2p2_cp_irq(void *input)

{

	int rc = 0;
@@ -709,6 +725,7 @@ static int dp_hdcp2p2_cp_irq(void *input) 


	kthread_queue_work(&ctrl->worker, &ctrl->link);



	dp_hdcp2p2_clear_cp_irq(ctrl);

	return 0;

error:

	return rc;